Lines Matching +full:mt7531 +full:- +full:dsa +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
21 #include <net/dsa.h>
73 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
92 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
96 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
105 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
124 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
127 dev_err(&bus->dev, in core_write_mmd_indirect()
135 struct mii_bus *bus = priv->bus; in core_write()
137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_write()
141 mutex_unlock(&bus->mdio_lock); in core_write()
147 struct mii_bus *bus = priv->bus; in core_rmw()
150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in core_rmw()
157 mutex_unlock(&bus->mdio_lock); in core_rmw()
175 struct mii_bus *bus = priv->bus; in mt7530_mii_write()
184 /* MT7530 uses 31 as the pseudo port */ in mt7530_mii_write()
185 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_write()
189 ret = bus->write(bus, 0x1f, r, lo); in mt7530_mii_write()
193 ret = bus->write(bus, 0x1f, 0x10, hi); in mt7530_mii_write()
196 dev_err(&bus->dev, in mt7530_mii_write()
204 struct mii_bus *bus = priv->bus; in mt7530_mii_read()
211 /* MT7530 uses 31 as the pseudo port */ in mt7530_mii_read()
212 ret = bus->write(bus, 0x1f, 0x1f, page); in mt7530_mii_read()
214 dev_err(&bus->dev, in mt7530_mii_read()
219 lo = bus->read(bus, 0x1f, r); in mt7530_mii_read()
220 hi = bus->read(bus, 0x1f, 0x10); in mt7530_mii_read()
228 struct mii_bus *bus = priv->bus; in mt7530_write()
230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_write()
234 mutex_unlock(&bus->mdio_lock); in mt7530_write()
240 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
246 struct mii_bus *bus = p->priv->bus; in _mt7530_read()
249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in _mt7530_read()
251 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
253 mutex_unlock(&bus->mdio_lock); in _mt7530_read()
271 struct mii_bus *bus = priv->bus; in mt7530_rmw()
274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_rmw()
281 mutex_unlock(&bus->mdio_lock); in mt7530_rmw()
311 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
320 return -EINVAL; in mt7530_fdb_cmd()
338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
342 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
386 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
392 dev_err(priv->dev, in mt7530_pad_clk_setup()
395 return -EINVAL; in mt7530_pad_clk_setup()
406 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
420 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
422 return -EINVAL; in mt7530_pad_clk_setup()
528 /* Step 1 : Disable MT7531 COREPLL */ in mt7531_pll_setup()
587 /* Step 6: Enable MT7531 PLL */ in mt7531_pll_setup()
601 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
607 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) in mt7530_phy_read() argument
609 struct mt7530_priv *priv = ds->priv; in mt7530_phy_read()
611 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read()
614 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, in mt7530_phy_write() argument
617 struct mt7530_priv *priv = ds->priv; in mt7530_phy_write()
619 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write()
623 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_read() argument
626 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_read()
633 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_read()
638 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
642 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
649 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
653 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
660 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
666 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_read()
672 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_write() argument
675 struct mii_bus *bus = priv->bus; in mt7531_ind_c45_phy_write()
682 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c45_phy_write()
687 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
691 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
698 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
702 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
709 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
714 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c45_phy_write()
720 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) in mt7531_ind_c22_phy_read() argument
722 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_read()
729 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_read()
734 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
738 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_read()
746 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
752 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_read()
758 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, in mt7531_ind_c22_phy_write() argument
761 struct mii_bus *bus = priv->bus; in mt7531_ind_c22_phy_write()
768 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7531_ind_c22_phy_write()
773 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
777 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_write()
785 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
790 mutex_unlock(&bus->mdio_lock); in mt7531_ind_c22_phy_write()
796 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) in mt7531_ind_phy_read() argument
798 struct mt7530_priv *priv = ds->priv; in mt7531_ind_phy_read()
804 ret = mt7531_ind_c45_phy_read(priv, port, devad, in mt7531_ind_phy_read()
807 ret = mt7531_ind_c22_phy_read(priv, port, regnum); in mt7531_ind_phy_read()
814 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, in mt7531_ind_phy_write() argument
817 struct mt7530_priv *priv = ds->priv; in mt7531_ind_phy_write()
823 ret = mt7531_ind_c45_phy_write(priv, port, devad, in mt7531_ind_phy_write()
827 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); in mt7531_ind_phy_write()
834 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, in mt7530_get_strings() argument
848 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, in mt7530_get_ethtool_stats() argument
851 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
858 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
861 if (mib->size == 2) { in mt7530_get_ethtool_stats()
869 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) in mt7530_get_sset_count() argument
879 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
883 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
890 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
892 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
896 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
899 /* Setup the MAC by default for the cpu port */ in mt7530_setup_port5()
903 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
910 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
911 priv->p5_intf_sel); in mt7530_setup_port5()
922 /* Don't set delay in DSA mode */ in mt7530_setup_port5()
923 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
939 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
940 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
942 priv->p5_interface = interface; in mt7530_setup_port5()
945 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
949 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) in mt753x_cpu_port_enable() argument
951 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
954 /* Setup max capability of CPU port at first */ in mt753x_cpu_port_enable()
955 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
956 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
961 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
962 mt7530_write(priv, MT7530_PVC_P(port), in mt753x_cpu_port_enable()
965 /* Unknown multicast frame forwarding to the cpu port */ in mt753x_cpu_port_enable()
966 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); in mt753x_cpu_port_enable()
968 /* Set CPU port number */ in mt753x_cpu_port_enable()
969 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt753x_cpu_port_enable()
970 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); in mt753x_cpu_port_enable()
972 /* CPU port gets connected to all user ports of in mt753x_cpu_port_enable()
975 mt7530_write(priv, MT7530_PCR_P(port), in mt753x_cpu_port_enable()
976 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
982 mt7530_port_enable(struct dsa_switch *ds, int port, in mt7530_port_enable() argument
985 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
987 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
989 /* Allow the user port gets connected to the cpu port and also in mt7530_port_enable()
990 * restore the port matrix if the port is the member of a certain in mt7530_port_enable()
993 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_enable()
994 priv->ports[port].enable = true; in mt7530_port_enable()
995 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_enable()
996 priv->ports[port].pm); in mt7530_port_enable()
997 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt7530_port_enable()
999 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1005 mt7530_port_disable(struct dsa_switch *ds, int port) in mt7530_port_disable() argument
1007 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1009 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1011 /* Clear up all port matrix which could be restored in the next in mt7530_port_disable()
1012 * enablement for the port. in mt7530_port_disable()
1014 priv->ports[port].enable = false; in mt7530_port_disable()
1015 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_disable()
1017 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt7530_port_disable()
1019 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1023 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) in mt7530_stp_state_set() argument
1025 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1047 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); in mt7530_stp_state_set()
1051 mt7530_port_bridge_join(struct dsa_switch *ds, int port, in mt7530_port_bridge_join() argument
1054 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1058 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1061 /* Add this port to the port matrix of the other ports in the in mt7530_port_bridge_join()
1062 * same bridge. If the port is disabled, port matrix is kept in mt7530_port_bridge_join()
1063 * and not being setup until the port becomes enabled. in mt7530_port_bridge_join()
1065 if (dsa_is_user_port(ds, i) && i != port) { in mt7530_port_bridge_join()
1066 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_join()
1068 if (priv->ports[i].enable) in mt7530_port_bridge_join()
1070 PCR_MATRIX(BIT(port))); in mt7530_port_bridge_join()
1071 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1077 /* Add the all other ports to this port matrix. */ in mt7530_port_bridge_join()
1078 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1079 mt7530_rmw(priv, MT7530_PCR_P(port), in mt7530_port_bridge_join()
1081 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1083 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1089 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_unaware() argument
1091 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1095 /* When a port is removed from the bridge, the port would be set up in mt7530_port_set_vlan_unaware()
1096 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_set_vlan_unaware()
1097 * port. in mt7530_port_set_vlan_unaware()
1099 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_unaware()
1101 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, in mt7530_port_set_vlan_unaware()
1113 /* CPU port also does the same thing until all user ports belonging to in mt7530_port_set_vlan_unaware()
1114 * the CPU port get out of VLAN filtering mode. in mt7530_port_set_vlan_unaware()
1118 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1125 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_aware() argument
1127 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1130 * table lookup. CPU port is set to fallback mode to let untagged in mt7530_port_set_vlan_aware()
1133 if (dsa_is_cpu_port(ds, port)) in mt7530_port_set_vlan_aware()
1134 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_aware()
1137 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_aware()
1140 /* Set the port as a user port which is to be able to recognize VID in mt7530_port_set_vlan_aware()
1143 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, in mt7530_port_set_vlan_aware()
1149 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, in mt7530_port_bridge_leave() argument
1152 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1155 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1158 /* Remove this port from the port matrix of the other ports in mt7530_port_bridge_leave()
1159 * in the same bridge. If the port is disabled, port matrix in mt7530_port_bridge_leave()
1160 * is kept and not being setup until the port becomes enabled. in mt7530_port_bridge_leave()
1162 if (dsa_is_user_port(ds, i) && i != port) { in mt7530_port_bridge_leave()
1163 if (dsa_to_port(ds, i)->bridge_dev != bridge) in mt7530_port_bridge_leave()
1165 if (priv->ports[i].enable) in mt7530_port_bridge_leave()
1167 PCR_MATRIX(BIT(port))); in mt7530_port_bridge_leave()
1168 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1172 /* Set the cpu port to be the only one in the port matrix of in mt7530_port_bridge_leave()
1173 * this port. in mt7530_port_bridge_leave()
1175 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1176 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_bridge_leave()
1178 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); in mt7530_port_bridge_leave()
1180 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1184 mt7530_port_fdb_add(struct dsa_switch *ds, int port, in mt7530_port_fdb_add() argument
1187 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1189 u8 port_mask = BIT(port); in mt7530_port_fdb_add()
1191 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1192 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1194 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1200 mt7530_port_fdb_del(struct dsa_switch *ds, int port, in mt7530_port_fdb_del() argument
1203 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1205 u8 port_mask = BIT(port); in mt7530_port_fdb_del()
1207 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1208 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1210 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1216 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, in mt7530_port_fdb_dump() argument
1219 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1225 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1234 if (_fdb.port_mask & BIT(port)) { in mt7530_port_fdb_dump()
1241 } while (--cnt && in mt7530_port_fdb_dump()
1245 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1264 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1270 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1271 return -EINVAL; in mt7530_vlan_cmd()
1278 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, in mt7530_port_vlan_filtering() argument
1286 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1288 * port and the corresponding CPU port is required the setup in mt7530_port_vlan_filtering()
1289 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1291 mt7530_port_set_vlan_aware(ds, port); in mt7530_port_vlan_filtering()
1294 mt7530_port_set_vlan_unaware(ds, port); in mt7530_port_vlan_filtering()
1301 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, in mt7530_port_vlan_prepare() argument
1316 new_members = entry->old_members | BIT(entry->port) | in mt7530_hw_vlan_add()
1320 * VLAN and joining the port as one of the port members. in mt7530_hw_vlan_add()
1326 * port inside the VLAN. in mt7530_hw_vlan_add()
1328 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : in mt7530_hw_vlan_add()
1331 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1332 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1334 /* CPU port is always taken as a tagged port for serving more than one in mt7530_hw_vlan_add()
1337 * DSA tag. in mt7530_hw_vlan_add()
1352 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1356 dev_err(priv->dev, in mt7530_hw_vlan_del()
1361 /* If certain member apart from CPU port is still alive in the VLAN, in mt7530_hw_vlan_del()
1387 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1397 mt7530_port_vlan_add(struct dsa_switch *ds, int port, in mt7530_port_vlan_add() argument
1400 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1401 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1403 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1406 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1408 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in mt7530_port_vlan_add()
1409 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); in mt7530_port_vlan_add()
1415 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_add()
1416 G0_PORT_VID(vlan->vid_end)); in mt7530_port_vlan_add()
1417 priv->ports[port].pvid = vlan->vid_end; in mt7530_port_vlan_add()
1420 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1424 mt7530_port_vlan_del(struct dsa_switch *ds, int port, in mt7530_port_vlan_del() argument
1428 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1431 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1433 pvid = priv->ports[port].pvid; in mt7530_port_vlan_del()
1434 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { in mt7530_port_vlan_del()
1435 mt7530_hw_vlan_entry_init(&target_entry, port, 0); in mt7530_port_vlan_del()
1439 /* PVID is being restored to the default whenever the PVID port in mt7530_port_vlan_del()
1446 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); in mt7530_port_vlan_del()
1447 priv->ports[port].pvid = pvid; in mt7530_port_vlan_del()
1449 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1466 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, in mt753x_port_mirror_add() argument
1470 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1475 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1476 return -EEXIST; in mt753x_port_mirror_add()
1478 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1480 /* MT7530 only supports one monitor port */ in mt753x_port_mirror_add()
1481 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1482 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1483 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1484 return -EEXIST; in mt753x_port_mirror_add()
1486 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1487 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1488 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1489 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1491 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_add()
1494 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1497 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1499 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_add()
1504 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, in mt753x_port_mirror_del() argument
1507 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1510 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_del()
1511 if (mirror->ingress) { in mt753x_port_mirror_del()
1513 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1516 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1518 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_del()
1520 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1521 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1522 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1523 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1528 mtk_get_tag_protocol(struct dsa_switch *ds, int port, in mtk_get_tag_protocol() argument
1531 struct mt7530_priv *priv = ds->priv; in mtk_get_tag_protocol()
1533 if (port != MT7530_CPU_PORT) { in mtk_get_tag_protocol()
1534 dev_warn(priv->dev, in mtk_get_tag_protocol()
1535 "port not matched with tagging CPU port\n"); in mtk_get_tag_protocol()
1545 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
1558 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; in mt7530_setup()
1559 ds->configure_vlan_while_not_filtering = true; in mt7530_setup()
1561 if (priv->id == ID_MT7530) { in mt7530_setup()
1562 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
1563 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
1565 dev_err(priv->dev, in mt7530_setup()
1570 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
1571 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
1573 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
1579 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
1582 if (priv->mcm) { in mt7530_setup()
1583 reset_control_assert(priv->rstc); in mt7530_setup()
1585 reset_control_deassert(priv->rstc); in mt7530_setup()
1587 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
1589 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
1597 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
1604 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
1605 return -ENODEV; in mt7530_setup()
1613 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ in mt7530_setup()
1619 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
1641 /* Setup port 5 */ in mt7530_setup()
1642 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
1646 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
1647 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
1648 if (ret && ret != -ENODEV) in mt7530_setup()
1654 "mediatek,eth-mac")) in mt7530_setup()
1661 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
1665 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
1667 if (ret && ret != -ENODEV) { in mt7530_setup()
1672 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
1674 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
1676 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
1697 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
1702 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
1705 if (priv->mcm) { in mt7531_setup()
1706 reset_control_assert(priv->rstc); in mt7531_setup()
1708 reset_control_deassert(priv->rstc); in mt7531_setup()
1710 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
1712 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
1720 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
1728 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
1729 return -ENODEV; in mt7531_setup()
1740 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
1742 /* Let ds->slave_mii_bus be able to access external phy. */ in mt7531_setup()
1748 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
1750 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
1751 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
1757 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
1758 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
1772 /* BPDU to CPU port */ in mt7531_setup()
1800 ds->configure_vlan_while_not_filtering = true; in mt7531_setup()
1811 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, in mt7530_phy_mode_supported() argument
1814 struct mt7530_priv *priv = ds->priv; in mt7530_phy_mode_supported()
1816 switch (port) { in mt7530_phy_mode_supported()
1818 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
1821 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ in mt7530_phy_mode_supported()
1822 if (!phy_interface_mode_is_rgmii(state->interface) && in mt7530_phy_mode_supported()
1823 state->interface != PHY_INTERFACE_MODE_MII && in mt7530_phy_mode_supported()
1824 state->interface != PHY_INTERFACE_MODE_GMII) in mt7530_phy_mode_supported()
1827 case 6: /* 1st cpu port */ in mt7530_phy_mode_supported()
1828 if (state->interface != PHY_INTERFACE_MODE_RGMII && in mt7530_phy_mode_supported()
1829 state->interface != PHY_INTERFACE_MODE_TRGMII) in mt7530_phy_mode_supported()
1833 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7530_phy_mode_supported()
1834 port); in mt7530_phy_mode_supported()
1841 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) in mt7531_is_rgmii_port() argument
1843 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
1847 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, in mt7531_phy_mode_supported() argument
1850 struct mt7530_priv *priv = ds->priv; in mt7531_phy_mode_supported()
1852 switch (port) { in mt7531_phy_mode_supported()
1854 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt7531_phy_mode_supported()
1857 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ in mt7531_phy_mode_supported()
1858 if (mt7531_is_rgmii_port(priv, port)) in mt7531_phy_mode_supported()
1859 return phy_interface_mode_is_rgmii(state->interface); in mt7531_phy_mode_supported()
1861 case 6: /* 1st cpu port supports sgmii/8023z only */ in mt7531_phy_mode_supported()
1862 if (state->interface != PHY_INTERFACE_MODE_SGMII && in mt7531_phy_mode_supported()
1863 !phy_interface_mode_is_8023z(state->interface)) in mt7531_phy_mode_supported()
1867 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, in mt7531_phy_mode_supported()
1868 port); in mt7531_phy_mode_supported()
1876 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, in mt753x_phy_mode_supported() argument
1879 struct mt7530_priv *priv = ds->priv; in mt753x_phy_mode_supported()
1881 return priv->info->phy_mode_supported(ds, port, state); in mt753x_phy_mode_supported()
1887 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
1889 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
1893 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7530_mac_config() argument
1896 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
1899 if (port != 5) in mt7530_mac_config()
1902 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
1907 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, in mt7531_rgmii_setup() argument
1913 if (!mt7531_is_rgmii_port(priv, port)) { in mt7531_rgmii_setup()
1914 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
1915 port); in mt7531_rgmii_setup()
1916 return -EINVAL; in mt7531_rgmii_setup()
1946 return -EINVAL; in mt7531_rgmii_setup()
1954 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, in mt7531_sgmii_validate() argument
1960 if (port == 6) { in mt7531_sgmii_validate()
1967 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, in mt7531_sgmii_link_up_force() argument
1971 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_link_up_force()
1980 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); in mt7531_sgmii_link_up_force()
1995 /* MT7531 SGMII 1G force mode can only work in full duplex mode, in mt7531_sgmii_link_up_force()
2002 mt7530_write(priv, MT7531_SGMII_MODE(port), val); in mt7531_sgmii_link_up_force()
2005 static bool mt753x_is_mac_port(u32 port) in mt753x_is_mac_port() argument
2007 return (port == 5 || port == 6); in mt753x_is_mac_port()
2010 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, in mt7531_sgmii_setup_mode_force() argument
2015 if (!mt753x_is_mac_port(port)) in mt7531_sgmii_setup_mode_force()
2016 return -EINVAL; in mt7531_sgmii_setup_mode_force()
2018 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), in mt7531_sgmii_setup_mode_force()
2021 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); in mt7531_sgmii_setup_mode_force()
2028 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); in mt7531_sgmii_setup_mode_force()
2030 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); in mt7531_sgmii_setup_mode_force()
2032 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex in mt7531_sgmii_setup_mode_force()
2035 mt7530_rmw(priv, MT7531_SGMII_MODE(port), in mt7531_sgmii_setup_mode_force()
2039 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); in mt7531_sgmii_setup_mode_force()
2044 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, in mt7531_sgmii_setup_mode_an() argument
2047 if (!mt753x_is_mac_port(port)) in mt7531_sgmii_setup_mode_an()
2048 return -EINVAL; in mt7531_sgmii_setup_mode_an()
2050 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), in mt7531_sgmii_setup_mode_an()
2053 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), in mt7531_sgmii_setup_mode_an()
2056 mt7530_set(priv, MT7531_SGMII_MODE(port), in mt7531_sgmii_setup_mode_an()
2060 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), in mt7531_sgmii_setup_mode_an()
2063 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); in mt7531_sgmii_setup_mode_an()
2065 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); in mt7531_sgmii_setup_mode_an()
2067 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); in mt7531_sgmii_setup_mode_an()
2072 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) in mt7531_sgmii_restart_an() argument
2074 struct mt7530_priv *priv = ds->priv; in mt7531_sgmii_restart_an()
2078 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); in mt7531_sgmii_restart_an()
2081 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); in mt7531_sgmii_restart_an()
2086 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7531_mac_config() argument
2089 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2093 if (!mt753x_is_mac_port(port)) { in mt7531_mac_config()
2094 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2095 return -EINVAL; in mt7531_mac_config()
2103 dp = dsa_to_port(ds, port); in mt7531_mac_config()
2104 phydev = dp->slave->phydev; in mt7531_mac_config()
2105 return mt7531_rgmii_setup(priv, port, interface, phydev); in mt7531_mac_config()
2107 return mt7531_sgmii_setup_mode_an(priv, port, interface); in mt7531_mac_config()
2112 return -EINVAL; in mt7531_mac_config()
2114 return mt7531_sgmii_setup_mode_force(priv, port, interface); in mt7531_mac_config()
2116 return -EINVAL; in mt7531_mac_config()
2119 return -EINVAL; in mt7531_mac_config()
2123 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_mac_config() argument
2126 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2128 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2132 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_phylink_mac_config() argument
2135 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2138 if (!mt753x_phy_mode_supported(ds, port, state)) in mt753x_phylink_mac_config()
2141 switch (port) { in mt753x_phylink_mac_config()
2143 if (state->interface != PHY_INTERFACE_MODE_GMII) in mt753x_phylink_mac_config()
2146 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ in mt753x_phylink_mac_config()
2147 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2150 if (mt753x_mac_config(ds, port, mode, state) < 0) in mt753x_phylink_mac_config()
2153 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2154 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
2156 case 6: /* 1st cpu port */ in mt753x_phylink_mac_config()
2157 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
2162 if (mt753x_mac_config(ds, port, mode, state) < 0) in mt753x_phylink_mac_config()
2165 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
2169 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
2170 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
2175 state->interface != PHY_INTERFACE_MODE_SGMII) { in mt753x_phylink_mac_config()
2176 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in mt753x_phylink_mac_config()
2181 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); in mt753x_phylink_mac_config()
2185 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
2188 if (port == 5 && dsa_is_user_port(ds, 5)) in mt753x_phylink_mac_config()
2192 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); in mt753x_phylink_mac_config()
2196 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) in mt753x_phylink_mac_an_restart() argument
2198 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_an_restart()
2200 if (!priv->info->mac_pcs_an_restart) in mt753x_phylink_mac_an_restart()
2203 priv->info->mac_pcs_an_restart(ds, port); in mt753x_phylink_mac_an_restart()
2206 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_down() argument
2210 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
2212 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt753x_phylink_mac_link_down()
2215 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, in mt753x_mac_pcs_link_up() argument
2219 struct mt7530_priv *priv = ds->priv; in mt753x_mac_pcs_link_up()
2221 if (!priv->info->mac_pcs_link_up) in mt753x_mac_pcs_link_up()
2224 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); in mt753x_mac_pcs_link_up()
2227 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_up() argument
2234 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
2237 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); in mt753x_phylink_mac_link_up()
2241 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
2266 mt7530_set(priv, MT7530_PMCR_P(port), mcr); in mt753x_phylink_mac_link_up()
2270 mt7531_cpu_port_config(struct dsa_switch *ds, int port) in mt7531_cpu_port_config() argument
2272 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
2277 switch (port) { in mt7531_cpu_port_config()
2279 if (mt7531_is_rgmii_port(priv, port)) in mt7531_cpu_port_config()
2284 priv->p5_interface = interface; in mt7531_cpu_port_config()
2289 priv->p6_interface = interface; in mt7531_cpu_port_config()
2292 return -EINVAL; in mt7531_cpu_port_config()
2300 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); in mt7531_cpu_port_config()
2303 mt7530_write(priv, MT7530_PMCR_P(port), in mt7531_cpu_port_config()
2304 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
2305 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, in mt7531_cpu_port_config()
2312 mt7530_mac_port_validate(struct dsa_switch *ds, int port, in mt7530_mac_port_validate() argument
2317 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, in mt7531_mac_port_validate() argument
2320 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_validate()
2322 mt7531_sgmii_validate(priv, port, supported); in mt7531_mac_port_validate()
2326 mt753x_phylink_validate(struct dsa_switch *ds, int port, in mt753x_phylink_validate() argument
2331 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_validate()
2333 if (state->interface != PHY_INTERFACE_MODE_NA && in mt753x_phylink_validate()
2334 !mt753x_phy_mode_supported(ds, port, state)) { in mt753x_phylink_validate()
2341 if (state->interface != PHY_INTERFACE_MODE_TRGMII && in mt753x_phylink_validate()
2342 !phy_interface_mode_is_8023z(state->interface)) { in mt753x_phylink_validate()
2350 /* This switch only supports 1G full-duplex. */ in mt753x_phylink_validate()
2351 if (state->interface != PHY_INTERFACE_MODE_MII) { in mt753x_phylink_validate()
2356 priv->info->mac_port_validate(ds, port, mask); in mt753x_phylink_validate()
2362 linkmode_and(state->advertising, state->advertising, mask); in mt753x_phylink_validate()
2371 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt7530_phylink_mac_link_state() argument
2374 struct mt7530_priv *priv = ds->priv; in mt7530_phylink_mac_link_state()
2377 if (port < 0 || port >= MT7530_NUM_PORTS) in mt7530_phylink_mac_link_state()
2378 return -EINVAL; in mt7530_phylink_mac_link_state()
2380 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); in mt7530_phylink_mac_link_state()
2382 state->link = (pmsr & PMSR_LINK); in mt7530_phylink_mac_link_state()
2383 state->an_complete = state->link; in mt7530_phylink_mac_link_state()
2384 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_phylink_mac_link_state()
2388 state->speed = SPEED_10; in mt7530_phylink_mac_link_state()
2391 state->speed = SPEED_100; in mt7530_phylink_mac_link_state()
2394 state->speed = SPEED_1000; in mt7530_phylink_mac_link_state()
2397 state->speed = SPEED_UNKNOWN; in mt7530_phylink_mac_link_state()
2401 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_phylink_mac_link_state()
2403 state->pause |= MLO_PAUSE_RX; in mt7530_phylink_mac_link_state()
2405 state->pause |= MLO_PAUSE_TX; in mt7530_phylink_mac_link_state()
2411 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, in mt7531_sgmii_pcs_get_state_an() argument
2417 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); in mt7531_sgmii_pcs_get_state_an()
2418 state->link = !!(status & MT7531_SGMII_LINK_STATUS); in mt7531_sgmii_pcs_get_state_an()
2419 if (state->interface == PHY_INTERFACE_MODE_SGMII && in mt7531_sgmii_pcs_get_state_an()
2421 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); in mt7531_sgmii_pcs_get_state_an()
2426 state->speed = SPEED_1000; in mt7531_sgmii_pcs_get_state_an()
2429 state->speed = SPEED_100; in mt7531_sgmii_pcs_get_state_an()
2432 state->speed = SPEED_10; in mt7531_sgmii_pcs_get_state_an()
2435 dev_err(priv->dev, "invalid sgmii PHY speed\n"); in mt7531_sgmii_pcs_get_state_an()
2436 state->link = false; in mt7531_sgmii_pcs_get_state_an()
2437 return -EINVAL; in mt7531_sgmii_pcs_get_state_an()
2441 state->duplex = DUPLEX_FULL; in mt7531_sgmii_pcs_get_state_an()
2443 state->duplex = DUPLEX_HALF; in mt7531_sgmii_pcs_get_state_an()
2450 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt7531_phylink_mac_link_state() argument
2453 struct mt7530_priv *priv = ds->priv; in mt7531_phylink_mac_link_state()
2455 if (state->interface == PHY_INTERFACE_MODE_SGMII) in mt7531_phylink_mac_link_state()
2456 return mt7531_sgmii_pcs_get_state_an(priv, port, state); in mt7531_phylink_mac_link_state()
2458 return -EOPNOTSUPP; in mt7531_phylink_mac_link_state()
2462 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_state() argument
2465 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_state()
2467 return priv->info->mac_port_get_state(ds, port, state); in mt753x_phylink_mac_link_state()
2473 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
2475 return priv->info->sw_setup(ds); in mt753x_setup()
2479 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) in mt753x_phy_read() argument
2481 struct mt7530_priv *priv = ds->priv; in mt753x_phy_read()
2483 return priv->info->phy_read(ds, port, regnum); in mt753x_phy_read()
2487 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) in mt753x_phy_write() argument
2489 struct mt7530_priv *priv = ds->priv; in mt753x_phy_write()
2491 return priv->info->phy_write(ds, port, regnum, val); in mt753x_phy_write()
2566 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
2577 dn = mdiodev->dev.of_node; in mt7530_probe()
2579 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in mt7530_probe()
2581 return -ENOMEM; in mt7530_probe()
2583 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe()
2584 if (!priv->ds) in mt7530_probe()
2585 return -ENOMEM; in mt7530_probe()
2587 priv->ds->dev = &mdiodev->dev; in mt7530_probe()
2588 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe()
2591 * casues a little bit differences on power-on sequence. in mt7530_probe()
2593 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); in mt7530_probe()
2594 if (priv->mcm) { in mt7530_probe()
2595 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); in mt7530_probe()
2597 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); in mt7530_probe()
2598 if (IS_ERR(priv->rstc)) { in mt7530_probe()
2599 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
2600 return PTR_ERR(priv->rstc); in mt7530_probe()
2607 priv->info = of_device_get_match_data(&mdiodev->dev); in mt7530_probe()
2608 if (!priv->info) in mt7530_probe()
2609 return -EINVAL; in mt7530_probe()
2614 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe()
2615 !priv->info->phy_read || !priv->info->phy_write || in mt7530_probe()
2616 !priv->info->phy_mode_supported || in mt7530_probe()
2617 !priv->info->mac_port_validate || in mt7530_probe()
2618 !priv->info->mac_port_get_state || !priv->info->mac_port_config) in mt7530_probe()
2619 return -EINVAL; in mt7530_probe()
2621 priv->id = priv->info->id; in mt7530_probe()
2623 if (priv->id == ID_MT7530) { in mt7530_probe()
2624 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); in mt7530_probe()
2625 if (IS_ERR(priv->core_pwr)) in mt7530_probe()
2626 return PTR_ERR(priv->core_pwr); in mt7530_probe()
2628 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); in mt7530_probe()
2629 if (IS_ERR(priv->io_pwr)) in mt7530_probe()
2630 return PTR_ERR(priv->io_pwr); in mt7530_probe()
2635 * the reset, otherwise memory-mapped register accessing used in mt7530_probe()
2638 if (!priv->mcm) { in mt7530_probe()
2639 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", in mt7530_probe()
2641 if (IS_ERR(priv->reset)) { in mt7530_probe()
2642 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); in mt7530_probe()
2643 return PTR_ERR(priv->reset); in mt7530_probe()
2647 priv->bus = mdiodev->bus; in mt7530_probe()
2648 priv->dev = &mdiodev->dev; in mt7530_probe()
2649 priv->ds->priv = priv; in mt7530_probe()
2650 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe()
2651 mutex_init(&priv->reg_mutex); in mt7530_probe()
2652 dev_set_drvdata(&mdiodev->dev, priv); in mt7530_probe()
2654 return dsa_register_switch(priv->ds); in mt7530_probe()
2660 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); in mt7530_remove()
2663 ret = regulator_disable(priv->core_pwr); in mt7530_remove()
2665 dev_err(priv->dev, in mt7530_remove()
2668 ret = regulator_disable(priv->io_pwr); in mt7530_remove()
2670 dev_err(priv->dev, "Failed to disable io pwr: %d\n", in mt7530_remove()
2673 dsa_unregister_switch(priv->ds); in mt7530_remove()
2674 mutex_destroy(&priv->reg_mutex); in mt7530_remove()