Lines Matching +full:0 +full:x40e
12 #define MT7530_ALL_MEMBERS 0xff
15 ID_MT7530 = 0,
22 #define TRGMII_BASE(x) (0x10000 + (x))
25 #define ETHSYS_CLKCFG0 0x2c
28 #define SYSC_REG_RSTCTRL 0x34
32 #define MT7530_MFC 0x10
33 #define BC_FFP(x) (((x) & 0xff) << 24)
34 #define UNM_FFP(x) (((x) & 0xff) << 16)
35 #define UNM_FFP_MASK UNM_FFP(~0)
36 #define UNU_FFP(x) (((x) & 0xff) << 8)
37 #define UNU_FFP_MASK UNU_FFP(~0)
40 #define CPU_MASK (0xf << 4)
42 #define MIRROR_PORT(x) ((x) & 0x7)
43 #define MIRROR_MASK 0x7
46 #define MT7531_CFC 0x4
51 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
61 #define MT753X_BPC 0x24
62 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
73 #define MT7530_ATA1 0x74
74 #define STATIC_EMP 0
76 #define MT7530_ATA2 0x78
79 #define MT7530_ATWD 0x7c
82 #define MT7530_ATC 0x80
83 #define ATC_HASH (((x) & 0xfff) << 16)
88 #define ATC_MAT(x) (((x) & 0xf) << 8)
89 #define ATC_MAT_MACTAB ATC_MAT(0)
92 MT7530_FDB_READ = 0,
100 #define MT7530_TSRA1 0x84
104 #define MAC_BYTE_3 0
105 #define MAC_BYTE_MASK 0xff
107 #define MT7530_TSRA2 0x88
110 #define CVID 0
111 #define CVID_MASK 0xfff
113 #define MT7530_ATRD 0x8C
115 #define AGE_TIMER_MASK 0xff
117 #define PORT_MAP_MASK 0xff
119 #define ENT_STATUS_MASK 0x3
122 #define MT7530_VTCR 0x90
125 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
126 #define VTCR_VID ((x) & 0xfff)
132 MT7530_VTCR_RD_VID = 0,
137 #define MT7530_VAWD1 0x94
144 #define PORT_MEM(x) (((x) & 0xff) << 16)
146 #define VLAN_VALID BIT(0)
148 #define PORT_MEM_MASK 0xff
150 #define MT7530_VAWD2 0x98
152 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
156 MT7530_VLAN_EGRESS_UNTAG = 0,
162 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
163 #define FID_PST(x) ((x) & 0x3)
164 #define FID_PST_MASK FID_PST(0x3)
167 MT7530_STP_DISABLED = 0,
175 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
178 #define PORT_VLAN(x) ((x) & 0x3)
182 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
196 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
197 #define PORT_PRI(x) (((x) & 0x7) << 24)
198 #define EG_TAG(x) (((x) & 0x3) << 28)
199 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
200 #define PCR_MATRIX_CLR PCR_MATRIX(0)
204 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
208 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
210 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
212 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
216 MT7530_VLAN_EG_DISABLED = 0,
221 MT7530_VLAN_USER = 0,
225 #define STAG_VPID (((x) & 0xffff) << 16)
228 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
229 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
230 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
234 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
235 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
248 #define PMCR_FORCE_LNK BIT(0)
276 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
283 #define PMSR_SPEED_10 0x00
286 #define PMSR_LINK BIT(0)
289 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
293 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
294 #define MT7530_MIB_CCR 0x4fe0
311 #define MT7531_SGMII_REG_BASE 0x5000
313 ((p) - 5) * 0x1000 + (r))
316 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
322 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
323 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
324 #define MT7531_SGMII_TX_CONFIG BIT(0)
327 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
334 #define MT7531_SGMII_FORCE_SPEED_10 0
338 MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
339 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
343 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
347 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
349 #define MT7531_RG_TPHY_SPEED_1_25G 0x0
353 #define MT7530_SYS_CTRL 0x7000
356 #define SYS_CTRL_REG_RST BIT(0)
359 #define MT7531_PHY_IAC 0x701C
361 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
362 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
363 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
364 #define MT7531_MDIO_ST_MASK (0x3 << 16)
365 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
366 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
367 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
368 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
369 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
370 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
373 MT7531_MDIO_ADDR = 0,
381 MT7531_MDIO_ST_CL45 = 0,
397 #define MT7531_CLKGEN_CTRL 0x7500
398 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
400 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
404 #define GP_MODE(x) (((x) & 0x3) << 1)
406 #define GP_CLK_EN BIT(0)
409 MT7531_GP_MODE_RGMII = 0,
415 MT7531_CLK_SKEW_NO_CHG = 0,
422 #define MT7530_HWTRAP 0x7800
428 #define MT7531_HWTRAP 0x7800
431 #define HWTRAP_XTAL_FSEL_40MHZ 0
439 #define MT7530_MHWTRAP 0x7804
449 #define MT7530_TOP_SIG_CTRL 0x7808
452 #define MT7531_TOP_SIG_SR 0x780c
454 #define PAD_MCM_SMI_EN BIT(0)
456 #define MT7530_IO_DRV_CR 0x7810
457 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
458 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
460 #define MT7531_CHIP_REV 0x781C
462 #define MT7531_PLLGP_EN 0x7820
465 #define SW_PLLGP BIT(0)
467 #define MT7530_P6ECR 0x7830
468 #define P6_INTF_MODE_MASK 0x3
469 #define P6_INTF_MODE(x) ((x) & 0x3)
471 #define MT7531_PLLGP_CR0 0x78a8
474 #define RG_COREPLL_POSDIV_M 0x3800000
476 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
477 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
480 #define MT7531_ANA_PLLGP_CR2 0x78b0
481 #define MT7531_ANA_PLLGP_CR5 0x78bc
484 #define MT7530_TRGMII_RCK_CTRL 0x7a00
487 #define DQSI1_TAP_MASK (0x7f << 8)
488 #define DQSI0_TAP_MASK 0x7f
489 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
490 #define DQSI0_TAP(x) ((x) & 0x7f)
492 #define MT7530_TRGMII_RCK_RTT 0x7a04
496 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
499 #define RD_TAP_MASK 0x7f
500 #define RD_TAP(x) ((x) & 0x7f)
502 #define MT7530_TRGMII_TXCTRL 0x7a40
507 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
508 #define TD_DM_DRVP(x) ((x) & 0xf)
509 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
511 #define MT7530_TRGMII_TCK_CTRL 0x7a78
512 #define TCK_TAP(x) (((x) & 0xf) << 8)
514 #define MT7530_P5RGMIIRXCR 0x7b00
516 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
518 #define MT7530_P5RGMIITXCR 0x7b04
519 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
522 #define MT7531_GPIO_MODE0 0x7c0c
523 #define MT7531_GPIO0_MASK GENMASK(3, 0)
526 #define MT7531_GPIO_MODE1 0x7c10
532 #define MT7530_CREV 0x7ffc
534 #define MT7530_ID 0x7530
536 #define MT7531_CREV 0x781C
537 #define CHIP_REV_M 0x0f
538 #define MT7531_ID 0x7531
541 #define CORE_PLL_GROUP2 0x401
545 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
547 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
548 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
550 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
552 #define CORE_PLL_GROUP4 0x403
559 #define MT753X_CTRL_PHY_ADDR 0
561 #define CORE_PLL_GROUP5 0x404
562 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
564 #define CORE_PLL_GROUP6 0x405
565 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
567 #define CORE_PLL_GROUP7 0x406
570 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
573 #define CORE_PLL_GROUP10 0x409
574 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
576 #define CORE_PLL_GROUP11 0x40a
577 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
579 #define CORE_GSWPLL_GRP1 0x40d
580 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
581 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
586 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
588 #define CORE_GSWPLL_GRP2 0x40e
589 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
590 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
592 #define CORE_TRGMII_GSW_CLK_CG 0x410
593 #define REG_GSWCK_EN BIT(0)
634 P5_DISABLED = 0,