Lines Matching +full:ar7100 +full:- +full:reset
1 // SPDX-License-Identifier: GPL-2.0
2 /* Atheros AR71xx built-in ethernet mac driver
11 * David Bauer <mail@david-bauer.net>
14 * Hauke Mehrtens <hauke@hauke-m.de>
15 * Johann Neuhauser <johann@it-neuhauser.de>
17 * Jo-Philipp Wich <jo@mein.io>
37 #include <linux/reset.h>
41 /* For our NAPI weight bigger does *NOT* mean better - it means more
42 * D-cache misses and lots more wasted cycles than we'll ever
75 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
244 { 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", },
245 { 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", },
246 { 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", },
247 { 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", },
248 { 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", },
249 { 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", },
320 /* "Cold" fields - not used in the data path. */
329 AR7100, enumerator
347 /* Critical data related to the per-packet data path are clustered
348 * early in this structure to help improve the D-cache footprint.
362 /* From this point onwards we're not looking at per-packet fields. */
388 return (desc->ctrl & DESC_EMPTY) != 0; in ag71xx_desc_empty()
393 return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE]; in ag71xx_ring_desc()
398 return fls(size - 1); in ag71xx_ring_size_order()
403 return ag->dcfg->type == type; in ag71xx_is()
408 iowrite32(value, ag->mac_base + reg); in ag71xx_wr()
410 (void)ioread32(ag->mac_base + reg); in ag71xx_wr()
415 return ioread32(ag->mac_base + reg); in ag71xx_rr()
422 r = ag->mac_base + reg; in ag71xx_sb()
432 r = ag->mac_base + reg; in ag71xx_cb()
453 strlcpy(info->driver, "ag71xx", sizeof(info->driver)); in ag71xx_get_drvinfo()
454 strlcpy(info->bus_info, of_node_full_name(ag->pdev->dev.of_node), in ag71xx_get_drvinfo()
455 sizeof(info->bus_info)); in ag71xx_get_drvinfo()
463 return phylink_ethtool_ksettings_get(ag->phylink, kset); in ag71xx_get_link_ksettings()
471 return phylink_ethtool_ksettings_set(ag->phylink, kset); in ag71xx_set_link_ksettings()
478 return phylink_ethtool_nway_reset(ag->phylink); in ag71xx_ethtool_nway_reset()
486 phylink_ethtool_get_pauseparam(ag->phylink, pause); in ag71xx_ethtool_get_pauseparam()
494 return phylink_ethtool_set_pauseparam(ag->phylink, pause); in ag71xx_ethtool_set_pauseparam()
524 return -EOPNOTSUPP; in ag71xx_ethtool_get_sset_count()
543 struct net_device *ndev = ag->ndev; in ag71xx_mdio_wait_busy()
560 return -ETIMEDOUT; in ag71xx_mdio_wait_busy()
565 struct ag71xx *ag = bus->priv; in ag71xx_mdio_mii_read()
585 netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n", in ag71xx_mdio_mii_read()
594 struct ag71xx *ag = bus->priv; in ag71xx_mdio_mii_write()
596 netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n", in ag71xx_mdio_mii_write()
624 ref_clock = clk_get_rate(ag->clk_mdio); in ag71xx_mdio_get_divider()
626 return -EINVAL; in ag71xx_mdio_get_divider()
649 return -ENOENT; in ag71xx_mdio_get_divider()
654 struct ag71xx *ag = bus->priv; in ag71xx_mdio_reset()
673 struct device *dev = &ag->pdev->dev; in ag71xx_mdio_probe()
674 struct net_device *ndev = ag->ndev; in ag71xx_mdio_probe()
679 np = dev->of_node; in ag71xx_mdio_probe()
680 ag->mii_bus = NULL; in ag71xx_mdio_probe()
682 ag->clk_mdio = devm_clk_get(dev, "mdio"); in ag71xx_mdio_probe()
683 if (IS_ERR(ag->clk_mdio)) { in ag71xx_mdio_probe()
685 return PTR_ERR(ag->clk_mdio); in ag71xx_mdio_probe()
688 err = clk_prepare_enable(ag->clk_mdio); in ag71xx_mdio_probe()
696 err = -ENOMEM; in ag71xx_mdio_probe()
700 ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio"); in ag71xx_mdio_probe()
701 if (IS_ERR(ag->mdio_reset)) { in ag71xx_mdio_probe()
702 netif_err(ag, probe, ndev, "Failed to get reset mdio.\n"); in ag71xx_mdio_probe()
703 err = PTR_ERR(ag->mdio_reset); in ag71xx_mdio_probe()
707 mii_bus->name = "ag71xx_mdio"; in ag71xx_mdio_probe()
708 mii_bus->read = ag71xx_mdio_mii_read; in ag71xx_mdio_probe()
709 mii_bus->write = ag71xx_mdio_mii_write; in ag71xx_mdio_probe()
710 mii_bus->reset = ag71xx_mdio_reset; in ag71xx_mdio_probe()
711 mii_bus->priv = ag; in ag71xx_mdio_probe()
712 mii_bus->parent = dev; in ag71xx_mdio_probe()
713 snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx); in ag71xx_mdio_probe()
715 if (!IS_ERR(ag->mdio_reset)) { in ag71xx_mdio_probe()
716 reset_control_assert(ag->mdio_reset); in ag71xx_mdio_probe()
718 reset_control_deassert(ag->mdio_reset); in ag71xx_mdio_probe()
728 ag->mii_bus = mii_bus; in ag71xx_mdio_probe()
733 clk_disable_unprepare(ag->clk_mdio); in ag71xx_mdio_probe()
739 if (ag->mii_bus) in ag71xx_mdio_remove()
740 mdiobus_unregister(ag->mii_bus); in ag71xx_mdio_remove()
741 clk_disable_unprepare(ag->clk_mdio); in ag71xx_mdio_remove()
757 timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start; in ag71xx_check_dma_stuck()
761 if (!netif_carrier_ok(ag->ndev)) in ag71xx_check_dma_stuck()
779 struct ag71xx_ring *ring = &ag->tx_ring; in ag71xx_tx_packets()
781 struct net_device *ndev = ag->ndev; in ag71xx_tx_packets()
785 ring_mask = BIT(ring->order) - 1; in ag71xx_tx_packets()
786 ring_size = BIT(ring->order); in ag71xx_tx_packets()
790 while (ring->dirty + n != ring->curr) { in ag71xx_tx_packets()
795 i = (ring->dirty + n) & ring_mask; in ag71xx_tx_packets()
797 skb = ring->buf[i].tx.skb; in ag71xx_tx_packets()
800 if (ag->dcfg->tx_hang_workaround && in ag71xx_tx_packets()
802 schedule_delayed_work(&ag->restart_work, in ag71xx_tx_packets()
810 desc->ctrl |= DESC_EMPTY; in ag71xx_tx_packets()
817 ring->buf[i].tx.skb = NULL; in ag71xx_tx_packets()
819 bytes_compl += ring->buf[i].tx.len; in ag71xx_tx_packets()
822 ring->dirty += n; in ag71xx_tx_packets()
826 n--; in ag71xx_tx_packets()
835 ag->ndev->stats.tx_bytes += bytes_compl; in ag71xx_tx_packets()
836 ag->ndev->stats.tx_packets += sent; in ag71xx_tx_packets()
838 netdev_completed_queue(ag->ndev, sent, bytes_compl); in ag71xx_tx_packets()
839 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4) in ag71xx_tx_packets()
840 netif_wake_queue(ag->ndev); in ag71xx_tx_packets()
843 cancel_delayed_work(&ag->restart_work); in ag71xx_tx_packets()
850 struct net_device *ndev = ag->ndev; in ag71xx_dma_wait_stop()
869 struct net_device *ndev = ag->ndev; in ag71xx_dma_reset()
883 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma); in ag71xx_dma_reset()
884 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma); in ag71xx_dma_reset()
926 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]); in ag71xx_hw_setup()
927 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]); in ag71xx_hw_setup()
952 struct net_device *dev = ag->ndev; in ag71xx_fast_reset()
963 reset_control_assert(ag->mac_reset); in ag71xx_fast_reset()
965 reset_control_deassert(ag->mac_reset); in ag71xx_fast_reset()
970 ag->tx_ring.curr = 0; in ag71xx_fast_reset()
971 ag->tx_ring.dirty = 0; in ag71xx_fast_reset()
972 netdev_reset_queue(ag->ndev); in ag71xx_fast_reset()
976 ag71xx_max_frame_len(ag->ndev->mtu)); in ag71xx_fast_reset()
979 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); in ag71xx_fast_reset()
982 ag71xx_hw_set_macaddr(ag, dev->dev_addr); in ag71xx_fast_reset()
993 netif_wake_queue(ag->ndev); in ag71xx_hw_start()
999 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); in ag71xx_mac_config()
1004 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) in ag71xx_mac_config()
1007 if (ag->tx_ring.desc_split) { in ag71xx_mac_config()
1008 ag->fifodata[2] &= 0xffff; in ag71xx_mac_config()
1009 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16; in ag71xx_mac_config()
1012 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]); in ag71xx_mac_config()
1019 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); in ag71xx_mac_validate()
1022 switch (state->interface) { in ag71xx_mac_validate()
1026 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) || in ag71xx_mac_validate()
1029 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) in ag71xx_mac_validate()
1033 if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) || in ag71xx_mac_validate()
1034 (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) || in ag71xx_mac_validate()
1035 (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1)) in ag71xx_mac_validate()
1039 if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0) in ag71xx_mac_validate()
1043 if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0) in ag71xx_mac_validate()
1047 if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) || in ag71xx_mac_validate()
1048 (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1)) in ag71xx_mac_validate()
1065 if (state->interface == PHY_INTERFACE_MODE_NA || in ag71xx_mac_validate()
1066 state->interface == PHY_INTERFACE_MODE_SGMII || in ag71xx_mac_validate()
1067 state->interface == PHY_INTERFACE_MODE_RGMII || in ag71xx_mac_validate()
1068 state->interface == PHY_INTERFACE_MODE_GMII) { in ag71xx_mac_validate()
1075 bitmap_and(state->advertising, state->advertising, mask, in ag71xx_mac_validate()
1086 state->link = 0; in ag71xx_mac_pcs_get_state()
1097 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); in ag71xx_mac_link_down()
1108 struct ag71xx *ag = netdev_priv(to_net_dev(config->dev)); in ag71xx_mac_link_up()
1168 ag->phylink_config.dev = &ag->ndev->dev; in ag71xx_phylink_setup()
1169 ag->phylink_config.type = PHYLINK_NETDEV; in ag71xx_phylink_setup()
1171 phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode, in ag71xx_phylink_setup()
1172 ag->phy_if_mode, &ag71xx_phylink_mac_ops); in ag71xx_phylink_setup()
1176 ag->phylink = phylink; in ag71xx_phylink_setup()
1182 struct ag71xx_ring *ring = &ag->tx_ring; in ag71xx_ring_tx_clean()
1183 int ring_mask = BIT(ring->order) - 1; in ag71xx_ring_tx_clean()
1185 struct net_device *ndev = ag->ndev; in ag71xx_ring_tx_clean()
1187 while (ring->curr != ring->dirty) { in ag71xx_ring_tx_clean()
1189 u32 i = ring->dirty & ring_mask; in ag71xx_ring_tx_clean()
1193 desc->ctrl = 0; in ag71xx_ring_tx_clean()
1194 ndev->stats.tx_errors++; in ag71xx_ring_tx_clean()
1197 if (ring->buf[i].tx.skb) { in ag71xx_ring_tx_clean()
1198 bytes_compl += ring->buf[i].tx.len; in ag71xx_ring_tx_clean()
1200 dev_kfree_skb_any(ring->buf[i].tx.skb); in ag71xx_ring_tx_clean()
1202 ring->buf[i].tx.skb = NULL; in ag71xx_ring_tx_clean()
1203 ring->dirty++; in ag71xx_ring_tx_clean()
1214 struct ag71xx_ring *ring = &ag->tx_ring; in ag71xx_ring_tx_init()
1215 int ring_size = BIT(ring->order); in ag71xx_ring_tx_init()
1216 int ring_mask = ring_size - 1; in ag71xx_ring_tx_init()
1222 desc->next = (u32)(ring->descs_dma + in ag71xx_ring_tx_init()
1225 desc->ctrl = DESC_EMPTY; in ag71xx_ring_tx_init()
1226 ring->buf[i].tx.skb = NULL; in ag71xx_ring_tx_init()
1232 ring->curr = 0; in ag71xx_ring_tx_init()
1233 ring->dirty = 0; in ag71xx_ring_tx_init()
1234 netdev_reset_queue(ag->ndev); in ag71xx_ring_tx_init()
1239 struct ag71xx_ring *ring = &ag->rx_ring; in ag71xx_ring_rx_clean()
1240 int ring_size = BIT(ring->order); in ag71xx_ring_rx_clean()
1243 if (!ring->buf) in ag71xx_ring_rx_clean()
1247 if (ring->buf[i].rx.rx_buf) { in ag71xx_ring_rx_clean()
1248 dma_unmap_single(&ag->pdev->dev, in ag71xx_ring_rx_clean()
1249 ring->buf[i].rx.dma_addr, in ag71xx_ring_rx_clean()
1250 ag->rx_buf_size, DMA_FROM_DEVICE); in ag71xx_ring_rx_clean()
1251 skb_free_frag(ring->buf[i].rx.rx_buf); in ag71xx_ring_rx_clean()
1257 return ag->rx_buf_size + in ag71xx_buffer_size()
1265 struct ag71xx_ring *ring = &ag->rx_ring; in ag71xx_fill_rx_buf()
1269 desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]); in ag71xx_fill_rx_buf()
1275 buf->rx.rx_buf = data; in ag71xx_fill_rx_buf()
1276 buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size, in ag71xx_fill_rx_buf()
1278 desc->data = (u32)buf->rx.dma_addr + offset; in ag71xx_fill_rx_buf()
1284 struct ag71xx_ring *ring = &ag->rx_ring; in ag71xx_ring_rx_init()
1285 struct net_device *ndev = ag->ndev; in ag71xx_ring_rx_init()
1286 int ring_mask = BIT(ring->order) - 1; in ag71xx_ring_rx_init()
1287 int ring_size = BIT(ring->order); in ag71xx_ring_rx_init()
1295 desc->next = (u32)(ring->descs_dma + in ag71xx_ring_rx_init()
1299 desc, desc->next); in ag71xx_ring_rx_init()
1305 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset, in ag71xx_ring_rx_init()
1307 ret = -ENOMEM; in ag71xx_ring_rx_init()
1311 desc->ctrl = DESC_EMPTY; in ag71xx_ring_rx_init()
1317 ring->curr = 0; in ag71xx_ring_rx_init()
1318 ring->dirty = 0; in ag71xx_ring_rx_init()
1325 struct ag71xx_ring *ring = &ag->rx_ring; in ag71xx_ring_rx_refill()
1326 int ring_mask = BIT(ring->order) - 1; in ag71xx_ring_rx_refill()
1327 int offset = ag->rx_buf_offset; in ag71xx_ring_rx_refill()
1331 for (; ring->curr - ring->dirty > 0; ring->dirty++) { in ag71xx_ring_rx_refill()
1335 i = ring->dirty & ring_mask; in ag71xx_ring_rx_refill()
1338 if (!ring->buf[i].rx.rx_buf && in ag71xx_ring_rx_refill()
1339 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset, in ag71xx_ring_rx_refill()
1343 desc->ctrl = DESC_EMPTY; in ag71xx_ring_rx_refill()
1350 netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n", in ag71xx_ring_rx_refill()
1358 struct ag71xx_ring *tx = &ag->tx_ring; in ag71xx_rings_init()
1359 struct ag71xx_ring *rx = &ag->rx_ring; in ag71xx_rings_init()
1362 ring_size = BIT(tx->order) + BIT(rx->order); in ag71xx_rings_init()
1363 tx_size = BIT(tx->order); in ag71xx_rings_init()
1365 tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL); in ag71xx_rings_init()
1366 if (!tx->buf) in ag71xx_rings_init()
1367 return -ENOMEM; in ag71xx_rings_init()
1369 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, in ag71xx_rings_init()
1371 &tx->descs_dma, GFP_KERNEL); in ag71xx_rings_init()
1372 if (!tx->descs_cpu) { in ag71xx_rings_init()
1373 kfree(tx->buf); in ag71xx_rings_init()
1374 tx->buf = NULL; in ag71xx_rings_init()
1375 return -ENOMEM; in ag71xx_rings_init()
1378 rx->buf = &tx->buf[tx_size]; in ag71xx_rings_init()
1379 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE; in ag71xx_rings_init()
1380 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE; in ag71xx_rings_init()
1388 struct ag71xx_ring *tx = &ag->tx_ring; in ag71xx_rings_free()
1389 struct ag71xx_ring *rx = &ag->rx_ring; in ag71xx_rings_free()
1392 ring_size = BIT(tx->order) + BIT(rx->order); in ag71xx_rings_free()
1394 if (tx->descs_cpu) in ag71xx_rings_free()
1395 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE, in ag71xx_rings_free()
1396 tx->descs_cpu, tx->descs_dma); in ag71xx_rings_free()
1398 kfree(tx->buf); in ag71xx_rings_free()
1400 tx->descs_cpu = NULL; in ag71xx_rings_free()
1401 rx->descs_cpu = NULL; in ag71xx_rings_free()
1402 tx->buf = NULL; in ag71xx_rings_free()
1403 rx->buf = NULL; in ag71xx_rings_free()
1412 netdev_reset_queue(ag->ndev); in ag71xx_rings_cleanup()
1422 reset_control_assert(ag->mac_reset); in ag71xx_hw_init()
1424 reset_control_deassert(ag->mac_reset); in ag71xx_hw_init()
1440 napi_enable(&ag->napi); in ag71xx_hw_enable()
1441 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); in ag71xx_hw_enable()
1442 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); in ag71xx_hw_enable()
1443 netif_start_queue(ag->ndev); in ag71xx_hw_enable()
1450 netif_stop_queue(ag->ndev); in ag71xx_hw_disable()
1455 napi_disable(&ag->napi); in ag71xx_hw_disable()
1456 del_timer_sync(&ag->oom_timer); in ag71xx_hw_disable()
1467 ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0); in ag71xx_open()
1474 max_frame_len = ag71xx_max_frame_len(ndev->mtu); in ag71xx_open()
1475 ag->rx_buf_size = in ag71xx_open()
1480 ag71xx_hw_set_macaddr(ag, ndev->dev_addr); in ag71xx_open()
1486 phylink_start(ag->phylink); in ag71xx_open()
1492 phylink_disconnect_phy(ag->phylink); in ag71xx_open()
1500 phylink_stop(ag->phylink); in ag71xx_stop()
1501 phylink_disconnect_phy(ag->phylink); in ag71xx_stop()
1512 ring_mask = BIT(ring->order) - 1; in ag71xx_fill_dma_desc()
1514 split = ring->desc_split; in ag71xx_fill_dma_desc()
1522 i = (ring->curr + ndesc) & ring_mask; in ag71xx_fill_dma_desc()
1526 return -1; in ag71xx_fill_dma_desc()
1535 cur_len -= 4; in ag71xx_fill_dma_desc()
1538 desc->data = addr; in ag71xx_fill_dma_desc()
1540 len -= cur_len; in ag71xx_fill_dma_desc()
1549 desc->ctrl = cur_len; in ag71xx_fill_dma_desc()
1565 ring = &ag->tx_ring; in ag71xx_hard_start_xmit()
1566 ring_mask = BIT(ring->order) - 1; in ag71xx_hard_start_xmit()
1567 ring_size = BIT(ring->order); in ag71xx_hard_start_xmit()
1569 if (skb->len <= 4) { in ag71xx_hard_start_xmit()
1574 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len, in ag71xx_hard_start_xmit()
1577 i = ring->curr & ring_mask; in ag71xx_hard_start_xmit()
1582 skb->len & ag->dcfg->desc_pktlen_mask); in ag71xx_hard_start_xmit()
1586 i = (ring->curr + n - 1) & ring_mask; in ag71xx_hard_start_xmit()
1587 ring->buf[i].tx.len = skb->len; in ag71xx_hard_start_xmit()
1588 ring->buf[i].tx.skb = skb; in ag71xx_hard_start_xmit()
1590 netdev_sent_queue(ndev, skb->len); in ag71xx_hard_start_xmit()
1594 desc->ctrl &= ~DESC_EMPTY; in ag71xx_hard_start_xmit()
1595 ring->curr += n; in ag71xx_hard_start_xmit()
1601 if (ring->desc_split) in ag71xx_hard_start_xmit()
1604 if (ring->curr - ring->dirty >= ring_size - ring_min) { in ag71xx_hard_start_xmit()
1617 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE); in ag71xx_hard_start_xmit()
1620 ndev->stats.tx_dropped++; in ag71xx_hard_start_xmit()
1630 napi_schedule(&ag->napi); in ag71xx_oom_timer_handler()
1639 schedule_delayed_work(&ag->restart_work, 1); in ag71xx_tx_timeout()
1651 phylink_stop(ag->phylink); in ag71xx_restart_work_func()
1652 phylink_start(ag->phylink); in ag71xx_restart_work_func()
1659 struct net_device *ndev = ag->ndev; in ag71xx_rx_packets()
1666 ring = &ag->rx_ring; in ag71xx_rx_packets()
1667 pktlen_mask = ag->dcfg->desc_pktlen_mask; in ag71xx_rx_packets()
1668 offset = ag->rx_buf_offset; in ag71xx_rx_packets()
1669 ring_mask = BIT(ring->order) - 1; in ag71xx_rx_packets()
1670 ring_size = BIT(ring->order); in ag71xx_rx_packets()
1673 limit, ring->curr, ring->dirty); in ag71xx_rx_packets()
1678 unsigned int i = ring->curr & ring_mask; in ag71xx_rx_packets()
1686 if ((ring->dirty + ring_size) == ring->curr) { in ag71xx_rx_packets()
1693 pktlen = desc->ctrl & pktlen_mask; in ag71xx_rx_packets()
1694 pktlen -= ETH_FCS_LEN; in ag71xx_rx_packets()
1696 dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr, in ag71xx_rx_packets()
1697 ag->rx_buf_size, DMA_FROM_DEVICE); in ag71xx_rx_packets()
1699 ndev->stats.rx_packets++; in ag71xx_rx_packets()
1700 ndev->stats.rx_bytes += pktlen; in ag71xx_rx_packets()
1702 skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag)); in ag71xx_rx_packets()
1704 skb_free_frag(ring->buf[i].rx.rx_buf); in ag71xx_rx_packets()
1712 ndev->stats.rx_dropped++; in ag71xx_rx_packets()
1715 skb->dev = ndev; in ag71xx_rx_packets()
1716 skb->ip_summed = CHECKSUM_NONE; in ag71xx_rx_packets()
1717 list_add_tail(&skb->list, &rx_list); in ag71xx_rx_packets()
1721 ring->buf[i].rx.rx_buf = NULL; in ag71xx_rx_packets()
1724 ring->curr++; in ag71xx_rx_packets()
1730 skb->protocol = eth_type_trans(skb, ndev); in ag71xx_rx_packets()
1734 ring->curr, ring->dirty, done); in ag71xx_rx_packets()
1742 struct ag71xx_ring *rx_ring = &ag->rx_ring; in ag71xx_poll()
1743 int rx_ring_size = BIT(rx_ring->order); in ag71xx_poll()
1744 struct net_device *ndev = ag->ndev; in ag71xx_poll()
1753 if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf) in ag71xx_poll()
1759 ndev->stats.rx_fifo_errors++; in ag71xx_poll()
1791 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); in ag71xx_poll()
1822 napi_schedule(&ag->napi); in ag71xx_interrupt()
1832 ndev->mtu = new_mtu; in ag71xx_change_mtu()
1834 ag71xx_max_frame_len(ndev->mtu)); in ag71xx_change_mtu()
1856 struct device_node *np = pdev->dev.of_node; in ag71xx_probe()
1865 return -ENODEV; in ag71xx_probe()
1867 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag)); in ag71xx_probe()
1869 return -ENOMEM; in ag71xx_probe()
1873 return -EINVAL; in ag71xx_probe()
1875 dcfg = of_device_get_match_data(&pdev->dev); in ag71xx_probe()
1877 return -EINVAL; in ag71xx_probe()
1880 ag->mac_idx = -1; in ag71xx_probe()
1882 if (ar71xx_addr_ar7100[i] == res->start) in ag71xx_probe()
1883 ag->mac_idx = i; in ag71xx_probe()
1886 if (ag->mac_idx < 0) { in ag71xx_probe()
1888 return -EINVAL; in ag71xx_probe()
1891 ag->clk_eth = devm_clk_get(&pdev->dev, "eth"); in ag71xx_probe()
1892 if (IS_ERR(ag->clk_eth)) { in ag71xx_probe()
1894 return PTR_ERR(ag->clk_eth); in ag71xx_probe()
1897 SET_NETDEV_DEV(ndev, &pdev->dev); in ag71xx_probe()
1899 ag->pdev = pdev; in ag71xx_probe()
1900 ag->ndev = ndev; in ag71xx_probe()
1901 ag->dcfg = dcfg; in ag71xx_probe()
1902 ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE); in ag71xx_probe()
1903 memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata)); in ag71xx_probe()
1905 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac"); in ag71xx_probe()
1906 if (IS_ERR(ag->mac_reset)) { in ag71xx_probe()
1907 netif_err(ag, probe, ndev, "missing mac reset\n"); in ag71xx_probe()
1908 return PTR_ERR(ag->mac_reset); in ag71xx_probe()
1911 ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); in ag71xx_probe()
1912 if (!ag->mac_base) in ag71xx_probe()
1913 return -ENOMEM; in ag71xx_probe()
1915 ndev->irq = platform_get_irq(pdev, 0); in ag71xx_probe()
1916 err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt, in ag71xx_probe()
1917 0x0, dev_name(&pdev->dev), ndev); in ag71xx_probe()
1920 ndev->irq); in ag71xx_probe()
1924 ndev->netdev_ops = &ag71xx_netdev_ops; in ag71xx_probe()
1925 ndev->ethtool_ops = &ag71xx_ethtool_ops; in ag71xx_probe()
1927 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func); in ag71xx_probe()
1928 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0); in ag71xx_probe()
1931 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT); in ag71xx_probe()
1933 ndev->min_mtu = 68; in ag71xx_probe()
1934 ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0); in ag71xx_probe()
1936 ag->rx_buf_offset = NET_SKB_PAD; in ag71xx_probe()
1937 if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130)) in ag71xx_probe()
1938 ag->rx_buf_offset += NET_IP_ALIGN; in ag71xx_probe()
1940 if (ag71xx_is(ag, AR7100)) { in ag71xx_probe()
1941 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT; in ag71xx_probe()
1944 ag->tx_ring.order = ag71xx_ring_size_order(tx_size); in ag71xx_probe()
1946 ag->stop_desc = dmam_alloc_coherent(&pdev->dev, in ag71xx_probe()
1948 &ag->stop_desc_dma, GFP_KERNEL); in ag71xx_probe()
1949 if (!ag->stop_desc) in ag71xx_probe()
1950 return -ENOMEM; in ag71xx_probe()
1952 ag->stop_desc->data = 0; in ag71xx_probe()
1953 ag->stop_desc->ctrl = 0; in ag71xx_probe()
1954 ag->stop_desc->next = (u32)ag->stop_desc_dma; in ag71xx_probe()
1958 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN); in ag71xx_probe()
1959 if (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) { in ag71xx_probe()
1961 eth_random_addr(ndev->dev_addr); in ag71xx_probe()
1964 err = of_get_phy_mode(np, &ag->phy_if_mode); in ag71xx_probe()
1966 netif_err(ag, probe, ndev, "missing phy-mode property in DT\n"); in ag71xx_probe()
1970 netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); in ag71xx_probe()
1972 err = clk_prepare_enable(ag->clk_eth); in ag71xx_probe()
2002 (unsigned long)ag->mac_base, ndev->irq, in ag71xx_probe()
2003 phy_modes(ag->phy_if_mode)); in ag71xx_probe()
2010 clk_disable_unprepare(ag->clk_eth); in ag71xx_probe()
2025 clk_disable_unprepare(ag->clk_eth); in ag71xx_remove()
2044 .type = AR7100,
2047 .desc_pktlen_mask = SZ_4K - 1,
2055 .desc_pktlen_mask = SZ_4K - 1,
2063 .desc_pktlen_mask = SZ_4K - 1,
2071 .desc_pktlen_mask = SZ_4K - 1,
2078 .max_frame_len = SZ_16K - 1,
2079 .desc_pktlen_mask = SZ_16K - 1,
2086 .max_frame_len = SZ_16K - 1,
2087 .desc_pktlen_mask = SZ_16K - 1,
2095 .desc_pktlen_mask = SZ_16K - 1,
2100 { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 },
2101 { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 },
2102 { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 },
2103 { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 },
2104 { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 },
2105 { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 },
2106 { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 },
2107 { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 },
2108 { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 },
2109 { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 },