Lines Matching full:plat
32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
204 static void common_default_data(struct plat_stmmacenet_data *plat) in common_default_data() argument
206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
207 plat->has_gmac = 1; in common_default_data()
208 plat->force_sf_dma_mode = 1; in common_default_data()
210 plat->mdio_bus_data->needs_reset = true; in common_default_data()
213 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
216 plat->unicast_filter_entries = 1; in common_default_data()
219 plat->maxmtu = JUMBO_LEN; in common_default_data()
222 plat->tx_queues_to_use = 1; in common_default_data()
223 plat->rx_queues_to_use = 1; in common_default_data()
226 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
227 plat->rx_queues_cfg[0].use_prio = false; in common_default_data()
230 plat->rx_queues_cfg[0].pkt_route = 0x0; in common_default_data()
234 struct plat_stmmacenet_data *plat) in intel_mgbe_common_data() argument
240 plat->phy_addr = -1; in intel_mgbe_common_data()
241 plat->clk_csr = 5; in intel_mgbe_common_data()
242 plat->has_gmac = 0; in intel_mgbe_common_data()
243 plat->has_gmac4 = 1; in intel_mgbe_common_data()
244 plat->force_sf_dma_mode = 0; in intel_mgbe_common_data()
245 plat->tso_en = 1; in intel_mgbe_common_data()
246 plat->sph_disable = 1; in intel_mgbe_common_data()
248 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in intel_mgbe_common_data()
250 for (i = 0; i < plat->rx_queues_to_use; i++) { in intel_mgbe_common_data()
251 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
252 plat->rx_queues_cfg[i].chan = i; in intel_mgbe_common_data()
255 plat->rx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
258 plat->rx_queues_cfg[i].pkt_route = 0x0; in intel_mgbe_common_data()
261 for (i = 0; i < plat->tx_queues_to_use; i++) { in intel_mgbe_common_data()
262 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
265 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
269 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; in intel_mgbe_common_data()
270 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; in intel_mgbe_common_data()
272 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; in intel_mgbe_common_data()
273 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
274 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
275 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
276 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
277 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
278 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
279 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
280 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()
282 plat->dma_cfg->pbl = 32; in intel_mgbe_common_data()
283 plat->dma_cfg->pblx8 = true; in intel_mgbe_common_data()
284 plat->dma_cfg->fixed_burst = 0; in intel_mgbe_common_data()
285 plat->dma_cfg->mixed_burst = 0; in intel_mgbe_common_data()
286 plat->dma_cfg->aal = 0; in intel_mgbe_common_data()
288 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), in intel_mgbe_common_data()
290 if (!plat->axi) in intel_mgbe_common_data()
293 plat->axi->axi_lpi_en = 0; in intel_mgbe_common_data()
294 plat->axi->axi_xit_frm = 0; in intel_mgbe_common_data()
295 plat->axi->axi_wr_osr_lmt = 1; in intel_mgbe_common_data()
296 plat->axi->axi_rd_osr_lmt = 1; in intel_mgbe_common_data()
297 plat->axi->axi_blen[0] = 4; in intel_mgbe_common_data()
298 plat->axi->axi_blen[1] = 8; in intel_mgbe_common_data()
299 plat->axi->axi_blen[2] = 16; in intel_mgbe_common_data()
301 plat->ptp_max_adj = plat->clk_ptp_rate; in intel_mgbe_common_data()
302 plat->eee_usecs_rate = plat->clk_ptp_rate; in intel_mgbe_common_data()
307 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, in intel_mgbe_common_data()
309 plat->clk_ptp_rate); in intel_mgbe_common_data()
311 if (IS_ERR(plat->stmmac_clk)) { in intel_mgbe_common_data()
313 plat->stmmac_clk = NULL; in intel_mgbe_common_data()
316 ret = clk_prepare_enable(plat->stmmac_clk); in intel_mgbe_common_data()
318 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_mgbe_common_data()
323 plat->multicast_filter_bins = HASH_TABLE_SIZE; in intel_mgbe_common_data()
326 plat->unicast_filter_entries = 1; in intel_mgbe_common_data()
329 plat->maxmtu = JUMBO_LEN; in intel_mgbe_common_data()
331 plat->vlan_fail_q_en = true; in intel_mgbe_common_data()
334 plat->vlan_fail_q = plat->rx_queues_to_use - 1; in intel_mgbe_common_data()
340 struct plat_stmmacenet_data *plat) in ehl_common_data() argument
342 plat->rx_queues_to_use = 8; in ehl_common_data()
343 plat->tx_queues_to_use = 8; in ehl_common_data()
344 plat->clk_ptp_rate = 200000000; in ehl_common_data()
346 return intel_mgbe_common_data(pdev, plat); in ehl_common_data()
350 struct plat_stmmacenet_data *plat) in ehl_sgmii_data() argument
352 plat->bus_id = 1; in ehl_sgmii_data()
353 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_sgmii_data()
355 plat->serdes_powerup = intel_serdes_powerup; in ehl_sgmii_data()
356 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_sgmii_data()
358 return ehl_common_data(pdev, plat); in ehl_sgmii_data()
366 struct plat_stmmacenet_data *plat) in ehl_rgmii_data() argument
368 plat->bus_id = 1; in ehl_rgmii_data()
369 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; in ehl_rgmii_data()
371 return ehl_common_data(pdev, plat); in ehl_rgmii_data()
379 struct plat_stmmacenet_data *plat) in ehl_pse0_common_data() argument
381 plat->bus_id = 2; in ehl_pse0_common_data()
382 plat->addr64 = 32; in ehl_pse0_common_data()
383 return ehl_common_data(pdev, plat); in ehl_pse0_common_data()
387 struct plat_stmmacenet_data *plat) in ehl_pse0_rgmii1g_data() argument
389 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse0_rgmii1g_data()
390 return ehl_pse0_common_data(pdev, plat); in ehl_pse0_rgmii1g_data()
398 struct plat_stmmacenet_data *plat) in ehl_pse0_sgmii1g_data() argument
400 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse0_sgmii1g_data()
401 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse0_sgmii1g_data()
402 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse0_sgmii1g_data()
403 return ehl_pse0_common_data(pdev, plat); in ehl_pse0_sgmii1g_data()
411 struct plat_stmmacenet_data *plat) in ehl_pse1_common_data() argument
413 plat->bus_id = 3; in ehl_pse1_common_data()
414 plat->addr64 = 32; in ehl_pse1_common_data()
415 return ehl_common_data(pdev, plat); in ehl_pse1_common_data()
419 struct plat_stmmacenet_data *plat) in ehl_pse1_rgmii1g_data() argument
421 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse1_rgmii1g_data()
422 return ehl_pse1_common_data(pdev, plat); in ehl_pse1_rgmii1g_data()
430 struct plat_stmmacenet_data *plat) in ehl_pse1_sgmii1g_data() argument
432 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse1_sgmii1g_data()
433 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse1_sgmii1g_data()
434 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse1_sgmii1g_data()
435 return ehl_pse1_common_data(pdev, plat); in ehl_pse1_sgmii1g_data()
443 struct plat_stmmacenet_data *plat) in tgl_common_data() argument
445 plat->rx_queues_to_use = 6; in tgl_common_data()
446 plat->tx_queues_to_use = 4; in tgl_common_data()
447 plat->clk_ptp_rate = 200000000; in tgl_common_data()
449 return intel_mgbe_common_data(pdev, plat); in tgl_common_data()
453 struct plat_stmmacenet_data *plat) in tgl_sgmii_data() argument
455 plat->bus_id = 1; in tgl_sgmii_data()
456 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_data()
457 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_data()
458 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_data()
459 return tgl_common_data(pdev, plat); in tgl_sgmii_data()
530 struct plat_stmmacenet_data *plat) in quark_default_data() argument
535 common_default_data(plat); in quark_default_data()
553 plat->bus_id = pci_dev_id(pdev); in quark_default_data()
554 plat->phy_addr = ret; in quark_default_data()
555 plat->phy_interface = PHY_INTERFACE_MODE_RMII; in quark_default_data()
557 plat->dma_cfg->pbl = 16; in quark_default_data()
558 plat->dma_cfg->pblx8 = true; in quark_default_data()
559 plat->dma_cfg->fixed_burst = 1; in quark_default_data()
586 struct plat_stmmacenet_data *plat; in intel_eth_pci_probe() local
594 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); in intel_eth_pci_probe()
595 if (!plat) in intel_eth_pci_probe()
598 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
599 sizeof(*plat->mdio_bus_data), in intel_eth_pci_probe()
601 if (!plat->mdio_bus_data) in intel_eth_pci_probe()
604 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), in intel_eth_pci_probe()
606 if (!plat->dma_cfg) in intel_eth_pci_probe()
623 plat->bsp_priv = intel_priv; in intel_eth_pci_probe()
626 ret = info->setup(pdev, plat); in intel_eth_pci_probe()
639 if (plat->eee_usecs_rate > 0) { in intel_eth_pci_probe()
642 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; in intel_eth_pci_probe()
646 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); in intel_eth_pci_probe()
649 clk_disable_unprepare(plat->stmmac_clk); in intel_eth_pci_probe()
650 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_eth_pci_probe()
672 clk_disable_unprepare(priv->plat->stmmac_clk); in intel_eth_pci_remove()
673 clk_unregister_fixed_rate(priv->plat->stmmac_clk); in intel_eth_pci_remove()