Lines Matching +full:filt +full:- +full:disable
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for NXP MCR20A 802.15.4 Wireless-PAN Networking controller
50 MCR20A_CCA_ED, // energy detect - CCA bit not active,
52 MCR20A_CCA_MODE1, // energy detect - CCA bit ACTIVE
53 MCR20A_CCA_MODE2, // 802.15.4 compliant signal detect - CCA bit ACTIVE
66 /* IEEE-802.15.4 defined constants (2.4 GHz logical channels) */
128 #define printdev(X) (&X->spi->dev)
452 lp->reg_msg.complete = NULL; in mcr20a_write_tx_buf_complete()
453 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1); in mcr20a_write_tx_buf_complete()
454 lp->reg_data[0] = MCR20A_XCVSEQ_TX; in mcr20a_write_tx_buf_complete()
455 lp->reg_xfer_data.len = 1; in mcr20a_write_tx_buf_complete()
457 ret = spi_async(lp->spi, &lp->reg_msg); in mcr20a_write_tx_buf_complete()
465 struct mcr20a_local *lp = hw->priv; in mcr20a_xmit()
469 lp->tx_skb = skb; in mcr20a_xmit()
472 skb->data, skb->len, 0); in mcr20a_xmit()
474 lp->is_tx = 1; in mcr20a_xmit()
476 lp->reg_msg.complete = NULL; in mcr20a_xmit()
477 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_PHY_CTRL1); in mcr20a_xmit()
478 lp->reg_data[0] = MCR20A_XCVSEQ_IDLE; in mcr20a_xmit()
479 lp->reg_xfer_data.len = 1; in mcr20a_xmit()
481 return spi_async(lp->spi, &lp->reg_msg); in mcr20a_xmit()
495 struct mcr20a_local *lp = hw->priv; in mcr20a_set_channel()
501 ret = regmap_write(lp->regmap_dar, DAR_PLL_INT0, PLL_INT[channel - 11]); in mcr20a_set_channel()
504 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_LSB, 0x00); in mcr20a_set_channel()
507 ret = regmap_write(lp->regmap_dar, DAR_PLL_FRAC0_MSB, in mcr20a_set_channel()
508 PLL_FRAC[channel - 11]); in mcr20a_set_channel()
518 struct mcr20a_local *lp = hw->priv; in mcr20a_start()
525 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_start()
531 enable_irq(lp->spi->irq); in mcr20a_start()
534 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL2, in mcr20a_start()
541 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_start()
552 struct mcr20a_local *lp = hw->priv; in mcr20a_stop()
557 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_stop()
560 /* disable irq */ in mcr20a_stop()
561 disable_irq(lp->spi->irq); in mcr20a_stop()
566 struct ieee802154_hw_addr_filt *filt, in mcr20a_set_hw_addr_filt() argument
569 struct mcr20a_local *lp = hw->priv; in mcr20a_set_hw_addr_filt()
574 u16 addr = le16_to_cpu(filt->short_addr); in mcr20a_set_hw_addr_filt()
576 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_LSB, addr); in mcr20a_set_hw_addr_filt()
577 regmap_write(lp->regmap_iar, IAR_MACSHORTADDRS0_MSB, addr >> 8); in mcr20a_set_hw_addr_filt()
581 u16 pan = le16_to_cpu(filt->pan_id); in mcr20a_set_hw_addr_filt()
583 regmap_write(lp->regmap_iar, IAR_MACPANID0_LSB, pan); in mcr20a_set_hw_addr_filt()
584 regmap_write(lp->regmap_iar, IAR_MACPANID0_MSB, pan >> 8); in mcr20a_set_hw_addr_filt()
590 memcpy(addr, &filt->ieee_addr, 8); in mcr20a_set_hw_addr_filt()
592 regmap_write(lp->regmap_iar, in mcr20a_set_hw_addr_filt()
597 if (filt->pan_coord) { in mcr20a_set_hw_addr_filt()
598 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_hw_addr_filt()
601 regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_hw_addr_filt()
609 /* -30 dBm to 10 dBm */
612 -3000, -2800, -2600, -2400, -2200, -2000, -1800, -1600, -1400,
613 -1200, -1000, -800, -600, -400, -200, 0, 200, 400, 600, 800, 1000
619 struct mcr20a_local *lp = hw->priv; in mcr20a_set_txpower()
624 for (i = 0; i < lp->hw->phy->supported.tx_powers_size; i++) { in mcr20a_set_txpower()
625 if (lp->hw->phy->supported.tx_powers[i] == mbm) in mcr20a_set_txpower()
626 return regmap_write(lp->regmap_dar, DAR_PA_PWR, in mcr20a_set_txpower()
630 return -EINVAL; in mcr20a_set_txpower()
640 struct mcr20a_local *lp = hw->priv; in mcr20a_set_cca_mode()
648 switch (cca->mode) { in mcr20a_set_cca_mode()
656 switch (cca->opt) { in mcr20a_set_cca_mode()
666 return -EINVAL; in mcr20a_set_cca_mode()
670 return -EINVAL; in mcr20a_set_cca_mode()
672 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_cca_mode()
680 ret = regmap_update_bits(lp->regmap_iar, IAR_CCA_CTRL, in mcr20a_set_cca_mode()
684 ret = regmap_update_bits(lp->regmap_iar, in mcr20a_set_cca_mode()
699 struct mcr20a_local *lp = hw->priv; in mcr20a_set_cca_ed_level()
704 for (i = 0; i < hw->phy->supported.cca_ed_levels_size; i++) { in mcr20a_set_cca_ed_level()
705 if (hw->phy->supported.cca_ed_levels[i] == mbm) in mcr20a_set_cca_ed_level()
706 return regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, i); in mcr20a_set_cca_ed_level()
715 struct mcr20a_local *lp = hw->priv; in mcr20a_set_promiscuous_mode()
727 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_promiscuous_mode()
733 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_set_promiscuous_mode()
738 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL4, in mcr20a_set_promiscuous_mode()
743 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_set_promiscuous_mode()
775 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_request_rx()
785 u8 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK; in mcr20a_handle_rx_read_buf_complete()
793 dev_vdbg(&lp->spi->dev, "corrupted frame received\n"); in mcr20a_handle_rx_read_buf_complete()
797 len = len - 2; /* get rid of frame check field */ in mcr20a_handle_rx_read_buf_complete()
803 __skb_put_data(skb, lp->rx_buf, len); in mcr20a_handle_rx_read_buf_complete()
804 ieee802154_rx_irqsafe(lp->hw, skb, lp->rx_lqi[0]); in mcr20a_handle_rx_read_buf_complete()
807 lp->rx_buf, len, 0); in mcr20a_handle_rx_read_buf_complete()
808 pr_debug("mcr20a rx: lqi: %02hhx\n", lp->rx_lqi[0]); in mcr20a_handle_rx_read_buf_complete()
824 len = lp->reg_data[0] & DAR_RX_FRAME_LENGTH_MASK; in mcr20a_handle_rx_read_len_complete()
828 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete; in mcr20a_handle_rx_read_len_complete()
829 lp->rx_header[0] = MCR20A_BURST_READ_PACKET_BUF; in mcr20a_handle_rx_read_len_complete()
830 lp->rx_xfer_buf.len = len; in mcr20a_handle_rx_read_len_complete()
832 ret = spi_async(lp->spi, &lp->rx_buf_msg); in mcr20a_handle_rx_read_len_complete()
841 lp->reg_msg.complete = mcr20a_handle_rx_read_len_complete; in mcr20a_handle_rx()
842 lp->reg_cmd[0] = MCR20A_READ_REG(DAR_RX_FRM_LEN); in mcr20a_handle_rx()
843 lp->reg_xfer_data.len = 1; in mcr20a_handle_rx()
845 return spi_async(lp->spi, &lp->reg_msg); in mcr20a_handle_rx()
853 ieee802154_xmit_complete(lp->hw, lp->tx_skb, false); in mcr20a_handle_tx_complete()
866 lp->tx_header[0] = MCR20A_BURST_WRITE_PACKET_BUF; in mcr20a_handle_tx()
868 lp->tx_len[0] = lp->tx_skb->len + 2; in mcr20a_handle_tx()
869 lp->tx_xfer_buf.tx_buf = lp->tx_skb->data; in mcr20a_handle_tx()
871 lp->tx_xfer_buf.len = lp->tx_skb->len + 1; in mcr20a_handle_tx()
873 ret = spi_async(lp->spi, &lp->tx_buf_msg); in mcr20a_handle_tx()
886 u8 seq_state = lp->irq_data[DAR_IRQ_STS1] & DAR_PHY_CTRL1_XCVSEQ_MASK; in mcr20a_irq_clean_complete()
890 enable_irq(lp->spi->irq); in mcr20a_irq_clean_complete()
893 lp->irq_data[DAR_IRQ_STS1], lp->irq_data[DAR_IRQ_STS2]); in mcr20a_irq_clean_complete()
898 if (lp->is_tx) { in mcr20a_irq_clean_complete()
899 lp->is_tx = 0; in mcr20a_irq_clean_complete()
910 if (lp->is_tx) { in mcr20a_irq_clean_complete()
912 lp->is_tx = 0; in mcr20a_irq_clean_complete()
922 if (lp->is_tx) { in mcr20a_irq_clean_complete()
938 regmap_update_bits_async(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_irq_status_complete()
941 lp->reg_msg.complete = mcr20a_irq_clean_complete; in mcr20a_irq_status_complete()
942 lp->reg_cmd[0] = MCR20A_WRITE_REG(DAR_IRQ_STS1); in mcr20a_irq_status_complete()
943 memcpy(lp->reg_data, lp->irq_data, MCR20A_IRQSTS_NUM); in mcr20a_irq_status_complete()
944 lp->reg_xfer_data.len = MCR20A_IRQSTS_NUM; in mcr20a_irq_status_complete()
946 ret = spi_async(lp->spi, &lp->reg_msg); in mcr20a_irq_status_complete()
959 lp->irq_header[0] = MCR20A_READ_REG(DAR_IRQ_STS1); in mcr20a_irq_isr()
961 ret = spi_async(lp->spi, &lp->irq_msg); in mcr20a_irq_isr()
973 struct ieee802154_hw *hw = lp->hw; in mcr20a_hw_setup()
974 struct wpan_phy *phy = lp->hw->phy; in mcr20a_hw_setup()
978 phy->symbol_duration = 16; in mcr20a_hw_setup()
979 phy->lifs_period = 40 * phy->symbol_duration; in mcr20a_hw_setup()
980 phy->sifs_period = 12 * phy->symbol_duration; in mcr20a_hw_setup()
982 hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | in mcr20a_hw_setup()
986 phy->flags = WPAN_PHY_FLAG_TXPOWER | WPAN_PHY_FLAG_CCA_ED_LEVEL | in mcr20a_hw_setup()
989 phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | in mcr20a_hw_setup()
991 phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND) | in mcr20a_hw_setup()
997 mcr20a_ed_levels[i] = -i * 100; in mcr20a_hw_setup()
1000 phy->supported.cca_ed_levels = mcr20a_ed_levels; in mcr20a_hw_setup()
1001 phy->supported.cca_ed_levels_size = ARRAY_SIZE(mcr20a_ed_levels); in mcr20a_hw_setup()
1003 phy->cca.mode = NL802154_CCA_ENERGY; in mcr20a_hw_setup()
1005 phy->supported.channels[0] = MCR20A_VALID_CHANNELS; in mcr20a_hw_setup()
1006 phy->current_page = 0; in mcr20a_hw_setup()
1008 phy->current_channel = 20; in mcr20a_hw_setup()
1009 phy->symbol_duration = 16; in mcr20a_hw_setup()
1010 phy->supported.tx_powers = mcr20a_powers; in mcr20a_hw_setup()
1011 phy->supported.tx_powers_size = ARRAY_SIZE(mcr20a_powers); in mcr20a_hw_setup()
1012 phy->cca_ed_level = phy->supported.cca_ed_levels[75]; in mcr20a_hw_setup()
1013 phy->transmit_power = phy->supported.tx_powers[0x0F]; in mcr20a_hw_setup()
1019 spi_message_init(&lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1020 lp->tx_buf_msg.context = lp; in mcr20a_setup_tx_spi_messages()
1021 lp->tx_buf_msg.complete = mcr20a_write_tx_buf_complete; in mcr20a_setup_tx_spi_messages()
1023 lp->tx_xfer_header.len = 1; in mcr20a_setup_tx_spi_messages()
1024 lp->tx_xfer_header.tx_buf = lp->tx_header; in mcr20a_setup_tx_spi_messages()
1026 lp->tx_xfer_len.len = 1; in mcr20a_setup_tx_spi_messages()
1027 lp->tx_xfer_len.tx_buf = lp->tx_len; in mcr20a_setup_tx_spi_messages()
1029 spi_message_add_tail(&lp->tx_xfer_header, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1030 spi_message_add_tail(&lp->tx_xfer_len, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1031 spi_message_add_tail(&lp->tx_xfer_buf, &lp->tx_buf_msg); in mcr20a_setup_tx_spi_messages()
1037 spi_message_init(&lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1038 lp->reg_msg.context = lp; in mcr20a_setup_rx_spi_messages()
1040 lp->reg_xfer_cmd.len = 1; in mcr20a_setup_rx_spi_messages()
1041 lp->reg_xfer_cmd.tx_buf = lp->reg_cmd; in mcr20a_setup_rx_spi_messages()
1042 lp->reg_xfer_cmd.rx_buf = lp->reg_cmd; in mcr20a_setup_rx_spi_messages()
1044 lp->reg_xfer_data.rx_buf = lp->reg_data; in mcr20a_setup_rx_spi_messages()
1045 lp->reg_xfer_data.tx_buf = lp->reg_data; in mcr20a_setup_rx_spi_messages()
1047 spi_message_add_tail(&lp->reg_xfer_cmd, &lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1048 spi_message_add_tail(&lp->reg_xfer_data, &lp->reg_msg); in mcr20a_setup_rx_spi_messages()
1050 spi_message_init(&lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1051 lp->rx_buf_msg.context = lp; in mcr20a_setup_rx_spi_messages()
1052 lp->rx_buf_msg.complete = mcr20a_handle_rx_read_buf_complete; in mcr20a_setup_rx_spi_messages()
1053 lp->rx_xfer_header.len = 1; in mcr20a_setup_rx_spi_messages()
1054 lp->rx_xfer_header.tx_buf = lp->rx_header; in mcr20a_setup_rx_spi_messages()
1055 lp->rx_xfer_header.rx_buf = lp->rx_header; in mcr20a_setup_rx_spi_messages()
1057 lp->rx_xfer_buf.rx_buf = lp->rx_buf; in mcr20a_setup_rx_spi_messages()
1059 lp->rx_xfer_lqi.len = 1; in mcr20a_setup_rx_spi_messages()
1060 lp->rx_xfer_lqi.rx_buf = lp->rx_lqi; in mcr20a_setup_rx_spi_messages()
1062 spi_message_add_tail(&lp->rx_xfer_header, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1063 spi_message_add_tail(&lp->rx_xfer_buf, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1064 spi_message_add_tail(&lp->rx_xfer_lqi, &lp->rx_buf_msg); in mcr20a_setup_rx_spi_messages()
1070 spi_message_init(&lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1071 lp->irq_msg.context = lp; in mcr20a_setup_irq_spi_messages()
1072 lp->irq_msg.complete = mcr20a_irq_status_complete; in mcr20a_setup_irq_spi_messages()
1073 lp->irq_xfer_header.len = 1; in mcr20a_setup_irq_spi_messages()
1074 lp->irq_xfer_header.tx_buf = lp->irq_header; in mcr20a_setup_irq_spi_messages()
1075 lp->irq_xfer_header.rx_buf = lp->irq_header; in mcr20a_setup_irq_spi_messages()
1077 lp->irq_xfer_data.len = MCR20A_IRQSTS_NUM; in mcr20a_setup_irq_spi_messages()
1078 lp->irq_xfer_data.rx_buf = lp->irq_data; in mcr20a_setup_irq_spi_messages()
1080 spi_message_add_tail(&lp->irq_xfer_header, &lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1081 spi_message_add_tail(&lp->irq_xfer_data, &lp->irq_msg); in mcr20a_setup_irq_spi_messages()
1093 /* Disable Tristate on COCO MISO for SPI reads */ in mcr20a_phy_init()
1094 ret = regmap_write(lp->regmap_iar, IAR_MISC_PAD_CTRL, 0x02); in mcr20a_phy_init()
1101 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS1, 0xEF); in mcr20a_phy_init()
1106 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS2, in mcr20a_phy_init()
1112 /* Disable all timer interrupts */ in mcr20a_phy_init()
1113 ret = regmap_write(lp->regmap_dar, DAR_IRQ_STS3, 0xFF); in mcr20a_phy_init()
1118 ret = regmap_update_bits(lp->regmap_dar, DAR_PHY_CTRL1, in mcr20a_phy_init()
1121 /* PHY_CTRL2 : disable all interrupts */ in mcr20a_phy_init()
1122 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL2, 0xFF); in mcr20a_phy_init()
1126 /* PHY_CTRL3 : disable all timers and remaining interrupts */ in mcr20a_phy_init()
1127 ret = regmap_write(lp->regmap_dar, DAR_PHY_CTRL3, in mcr20a_phy_init()
1136 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, in mcr20a_phy_init()
1144 ret = regmap_write(lp->regmap_iar, IAR_RX_FRAME_FILTER, in mcr20a_phy_init()
1156 ret = regmap_write(lp->regmap_dar, DAR_OVERWRITE_VER, in mcr20a_phy_init()
1162 ret = regmap_multi_reg_write(lp->regmap_iar, mar20a_iar_overwrites, in mcr20a_phy_init()
1174 ret = regmap_write(lp->regmap_dar, DAR_SRC_CTRL, phy_reg); in mcr20a_phy_init()
1181 ret = regmap_read(lp->regmap_iar, IAR_DUAL_PAN_CTRL, &phy_reg); in mcr20a_phy_init()
1191 ret = regmap_write(lp->regmap_iar, IAR_DUAL_PAN_CTRL, phy_reg); in mcr20a_phy_init()
1195 /* Set CCA threshold to -75 dBm */ in mcr20a_phy_init()
1196 ret = regmap_write(lp->regmap_iar, IAR_CCA1_THRESH, 0x4B); in mcr20a_phy_init()
1201 ret = regmap_write(lp->regmap_iar, IAR_TMR_PRESCALE, 0x05); in mcr20a_phy_init()
1206 ret = regmap_update_bits(lp->regmap_dar, DAR_PWR_MODES, in mcr20a_phy_init()
1212 /* Disable clk_out */ in mcr20a_phy_init()
1213 ret = regmap_update_bits(lp->regmap_dar, DAR_CLK_OUT_CTRL, in mcr20a_phy_init()
1231 int ret = -ENOMEM; in mcr20a_probe()
1233 dev_dbg(&spi->dev, "%s\n", __func__); in mcr20a_probe()
1235 if (!spi->irq) { in mcr20a_probe()
1236 dev_err(&spi->dev, "no IRQ specified\n"); in mcr20a_probe()
1237 return -EINVAL; in mcr20a_probe()
1240 rst_b = devm_gpiod_get(&spi->dev, "rst_b", GPIOD_OUT_HIGH); in mcr20a_probe()
1243 if (ret != -EPROBE_DEFER) in mcr20a_probe()
1244 dev_err(&spi->dev, "Failed to get 'rst_b' gpio: %d", ret); in mcr20a_probe()
1258 dev_crit(&spi->dev, "ieee802154_alloc_hw failed\n"); in mcr20a_probe()
1263 lp = hw->priv; in mcr20a_probe()
1264 lp->hw = hw; in mcr20a_probe()
1265 lp->spi = spi; in mcr20a_probe()
1268 hw->parent = &spi->dev; in mcr20a_probe()
1269 ieee802154_random_extended_addr(&hw->phy->perm_extended_addr); in mcr20a_probe()
1272 lp->buf = devm_kzalloc(&spi->dev, SPI_COMMAND_BUFFER, GFP_KERNEL); in mcr20a_probe()
1274 if (!lp->buf) { in mcr20a_probe()
1275 ret = -ENOMEM; in mcr20a_probe()
1284 lp->regmap_dar = devm_regmap_init_spi(spi, &mcr20a_dar_regmap); in mcr20a_probe()
1285 if (IS_ERR(lp->regmap_dar)) { in mcr20a_probe()
1286 ret = PTR_ERR(lp->regmap_dar); in mcr20a_probe()
1287 dev_err(&spi->dev, "Failed to allocate dar map: %d\n", in mcr20a_probe()
1292 lp->regmap_iar = devm_regmap_init_spi(spi, &mcr20a_iar_regmap); in mcr20a_probe()
1293 if (IS_ERR(lp->regmap_iar)) { in mcr20a_probe()
1294 ret = PTR_ERR(lp->regmap_iar); in mcr20a_probe()
1295 dev_err(&spi->dev, "Failed to allocate iar map: %d\n", ret); in mcr20a_probe()
1305 dev_crit(&spi->dev, "mcr20a_phy_init failed\n"); in mcr20a_probe()
1309 irq_type = irq_get_trigger_type(spi->irq); in mcr20a_probe()
1313 ret = devm_request_irq(&spi->dev, spi->irq, mcr20a_irq_isr, in mcr20a_probe()
1314 irq_type, dev_name(&spi->dev), lp); in mcr20a_probe()
1316 dev_err(&spi->dev, "could not request_irq for mcr20a\n"); in mcr20a_probe()
1317 ret = -ENODEV; in mcr20a_probe()
1322 disable_irq(spi->irq); in mcr20a_probe()
1326 dev_crit(&spi->dev, "ieee802154_register_hw failed\n"); in mcr20a_probe()
1333 ieee802154_free_hw(lp->hw); in mcr20a_probe()
1342 dev_dbg(&spi->dev, "%s\n", __func__); in mcr20a_remove()
1344 ieee802154_unregister_hw(lp->hw); in mcr20a_remove()
1345 ieee802154_free_hw(lp->hw); in mcr20a_remove()