1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <linux/mdio-mux.h>
77 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_recalc_rate()
87 	u32 val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
91 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
95 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_enable()
102 	return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val,  in g12a_ephy_pll_enable()
111 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_disable()
114 	writel(val, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_disable()
122 	val = readl(pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_is_enabled()
132 	writel(0x29c0040a, pll->base + ETH_PLL_CTL0);  in g12a_ephy_pll_init()
133 	writel(0x927e0000, pll->base + ETH_PLL_CTL1);  in g12a_ephy_pll_init()
134 	writel(0xac5f49e5, pll->base + ETH_PLL_CTL2);  in g12a_ephy_pll_init()
135 	writel(0x00000000, pll->base + ETH_PLL_CTL3);  in g12a_ephy_pll_init()
136 	writel(0x00000000, pll->base + ETH_PLL_CTL4);  in g12a_ephy_pll_init()
137 	writel(0x20200000, pll->base + ETH_PLL_CTL5);  in g12a_ephy_pll_init()
138 	writel(0x0000c002, pll->base + ETH_PLL_CTL6);  in g12a_ephy_pll_init()
139 	writel(0x00000023, pll->base + ETH_PLL_CTL7);  in g12a_ephy_pll_init()
158 	if (!priv->pll_is_enabled) {  in g12a_enable_internal_mdio()
159 		ret = clk_prepare_enable(priv->pll);  in g12a_enable_internal_mdio()
164 	priv->pll_is_enabled = true;  in g12a_enable_internal_mdio()
167 	writel(EPHY_G12A_ID, priv->regs + ETH_PHY_CNTL0);  in g12a_enable_internal_mdio()
169 	/* Make sure we get a 0 -> 1 transition on the enable bit */  in g12a_enable_internal_mdio()
175 	writel(value, priv->regs + ETH_PHY_CNTL1);  in g12a_enable_internal_mdio()
179 	       priv->regs + ETH_PHY_CNTL2);  in g12a_enable_internal_mdio()
182 	writel(value, priv->regs + ETH_PHY_CNTL1);  in g12a_enable_internal_mdio()
192 	/* Reset the mdio bus mux */  in g12a_enable_external_mdio()
193 	writel_relaxed(0x0, priv->regs + ETH_PHY_CNTL2);  in g12a_enable_external_mdio()
196 	if (priv->pll_is_enabled) {  in g12a_enable_external_mdio()
197 		clk_disable_unprepare(priv->pll);  in g12a_enable_external_mdio()
198 		priv->pll_is_enabled = false;  in g12a_enable_external_mdio()
218 		return -EINVAL;  in g12a_mdio_switch_fn()
223 	{ .compatible = "amlogic,g12a-mdio-mux", },
234 	struct clk_mux *mux;  in g12a_ephy_glue_clk_register()  local
239 	/* get the mux parents */  in g12a_ephy_glue_clk_register()
246 			if (PTR_ERR(clk) != -EPROBE_DEFER)  in g12a_ephy_glue_clk_register()
254 	/* create the input mux */  in g12a_ephy_glue_clk_register()
255 	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);  in g12a_ephy_glue_clk_register()
256 	if (!mux)  in g12a_ephy_glue_clk_register()
257 		return -ENOMEM;  in g12a_ephy_glue_clk_register()
259 	name = kasprintf(GFP_KERNEL, "%s#mux", dev_name(dev));  in g12a_ephy_glue_clk_register()
261 		return -ENOMEM;  in g12a_ephy_glue_clk_register()
269 	mux->reg = priv->regs + ETH_PLL_CTL0;  in g12a_ephy_glue_clk_register()
270 	mux->shift = __ffs(PLL_CTL0_SEL);  in g12a_ephy_glue_clk_register()
271 	mux->mask = PLL_CTL0_SEL >> mux->shift;  in g12a_ephy_glue_clk_register()
272 	mux->hw.init = &init;  in g12a_ephy_glue_clk_register()
274 	clk = devm_clk_register(dev, &mux->hw);  in g12a_ephy_glue_clk_register()
277 		dev_err(dev, "failed to register input mux\n");  in g12a_ephy_glue_clk_register()
284 		return -ENOMEM;  in g12a_ephy_glue_clk_register()
288 		return -ENOMEM;  in g12a_ephy_glue_clk_register()
297 	pll->base = priv->regs;  in g12a_ephy_glue_clk_register()
298 	pll->hw.init = &init;  in g12a_ephy_glue_clk_register()
300 	clk = devm_clk_register(dev, &pll->hw);  in g12a_ephy_glue_clk_register()
303 		dev_err(dev, "failed to register input mux\n");  in g12a_ephy_glue_clk_register()
307 	priv->pll = clk;  in g12a_ephy_glue_clk_register()
314 	struct device *dev = &pdev->dev;  in g12a_mdio_mux_probe()
320 		return -ENOMEM;  in g12a_mdio_mux_probe()
324 	priv->regs = devm_platform_ioremap_resource(pdev, 0);  in g12a_mdio_mux_probe()
325 	if (IS_ERR(priv->regs))  in g12a_mdio_mux_probe()
326 		return PTR_ERR(priv->regs);  in g12a_mdio_mux_probe()
328 	priv->pclk = devm_clk_get(dev, "pclk");  in g12a_mdio_mux_probe()
329 	if (IS_ERR(priv->pclk)) {  in g12a_mdio_mux_probe()
330 		ret = PTR_ERR(priv->pclk);  in g12a_mdio_mux_probe()
331 		if (ret != -EPROBE_DEFER)  in g12a_mdio_mux_probe()
337 	ret = clk_prepare_enable(priv->pclk);  in g12a_mdio_mux_probe()
348 	ret = mdio_mux_init(dev, dev->of_node, g12a_mdio_switch_fn,  in g12a_mdio_mux_probe()
349 			    &priv->mux_handle, dev, NULL);  in g12a_mdio_mux_probe()
351 		if (ret != -EPROBE_DEFER)  in g12a_mdio_mux_probe()
352 			dev_err(dev, "mdio multiplexer init failed: %d", ret);  in g12a_mdio_mux_probe()
359 	clk_disable_unprepare(priv->pclk);  in g12a_mdio_mux_probe()
367 	mdio_mux_uninit(priv->mux_handle);  in g12a_mdio_mux_remove()
369 	if (priv->pll_is_enabled)  in g12a_mdio_mux_remove()
370 		clk_disable_unprepare(priv->pll);  in g12a_mdio_mux_remove()
372 	clk_disable_unprepare(priv->pclk);  in g12a_mdio_mux_remove()
381 		.name	= "g12a-mdio_mux",
387 MODULE_DESCRIPTION("Amlogic G12a MDIO multiplexer driver");