Lines Matching +full:0 +full:xfffffff0
16 #define DP83822_PHY_ID 0x2000a240
17 #define DP83825S_PHY_ID 0x2000a140
18 #define DP83825I_PHY_ID 0x2000a150
19 #define DP83825CM_PHY_ID 0x2000a160
20 #define DP83825CS_PHY_ID 0x2000a170
21 #define DP83826C_PHY_ID 0x2000a130
22 #define DP83826NC_PHY_ID 0x2000a110
24 #define DP83822_DEVADDR 0x1f
26 #define MII_DP83822_CTRL_2 0x0a
27 #define MII_DP83822_PHYSTS 0x10
28 #define MII_DP83822_PHYSCR 0x11
29 #define MII_DP83822_MISR1 0x12
30 #define MII_DP83822_MISR2 0x13
31 #define MII_DP83822_FCSCR 0x14
32 #define MII_DP83822_RCSR 0x17
33 #define MII_DP83822_RESET_CTRL 0x1f
34 #define MII_DP83822_GENCFG 0x465
35 #define MII_DP83822_SOR1 0x467
38 #define DP83822_SIG_DET_LOW BIT(0)
49 #define DP83822_PHYSTS_LINK BIT(0)
52 #define DP83822_PHYSCR_INT_OE BIT(0) /* Interrupt Output Enable */
56 #define DP83822_RX_ERR_HF_INT_EN BIT(0)
66 #define DP83822_JABBER_DET_INT_EN BIT(0)
79 #define MII_DP83822_RXSOP1 0x04a5
80 #define MII_DP83822_RXSOP2 0x04a6
81 #define MII_DP83822_RXSOP3 0x04a7
84 #define MII_DP83822_WOL_CFG 0x04a0
85 #define MII_DP83822_WOL_STAT 0x04a1
86 #define MII_DP83822_WOL_DA1 0x04a2
87 #define MII_DP83822_WOL_DA2 0x04a3
88 #define MII_DP83822_WOL_DA3 0x04a4
91 #define DP83822_WOL_MAGIC_EN BIT(0)
102 #define DP83822_STRAP_MODE1 0
103 #define DP83822_STRAP_MODE2 BIT(0)
105 #define DP83822_STRAP_MODE4 GENMASK(1, 0)
127 if (err < 0) in dp83822_ack_interrupt()
131 if (err < 0) in dp83822_ack_interrupt()
134 return 0; in dp83822_ack_interrupt()
150 /* MAC addresses start with byte 5, but stored in mac[0]. in dp83822_set_wol()
151 * 822 PHYs store bytes 4|5, 2|3, 0|1 in dp83822_set_wol()
154 (mac[1] << 8) | mac[0]); in dp83822_set_wol()
170 (wol->sopass[1] << 8) | wol->sopass[0]); in dp83822_set_wol()
203 wol->wolopts = 0; in dp83822_get_wol()
213 wol->sopass[0] = (sopass_val & 0xff); in dp83822_get_wol()
218 wol->sopass[2] = (sopass_val & 0xff); in dp83822_get_wol()
223 wol->sopass[4] = (sopass_val & 0xff); in dp83822_get_wol()
229 /* WoL is not enabled so set wolopts to 0 */ in dp83822_get_wol()
231 wol->wolopts = 0; in dp83822_get_wol()
243 if (misr_status < 0) in dp83822_config_intr()
258 if (err < 0) in dp83822_config_intr()
262 if (misr_status < 0) in dp83822_config_intr()
277 if (err < 0) in dp83822_config_intr()
281 if (physcr_status < 0) in dp83822_config_intr()
287 err = phy_write(phydev, MII_DP83822_MISR1, 0); in dp83822_config_intr()
288 if (err < 0) in dp83822_config_intr()
291 err = phy_write(phydev, MII_DP83822_MISR2, 0); in dp83822_config_intr()
292 if (err < 0) in dp83822_config_intr()
296 if (physcr_status < 0) in dp83822_config_intr()
325 if (ctrl2 < 0) in dp83822_read_status()
331 if (ret < 0) in dp83822_read_status()
341 if (status < 0) in dp83822_read_status()
354 return 0; in dp83822_read_status()
364 int err = 0; in dp83822_config_init()
368 rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, in dp83822_config_init()
371 if (rx_int_delay <= 0) in dp83822_config_init()
372 rgmii_delay = 0; in dp83822_config_init()
376 tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, in dp83822_config_init()
378 if (tx_int_delay <= 0) in dp83822_config_init()
394 if (err < 0) in dp83822_config_init()
416 if (bmcr < 0) in dp83822_config_init()
420 err = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); in dp83822_config_init()
421 if (err < 0) in dp83822_config_init()
435 if (err < 0) in dp83822_config_init()
459 if (err < 0) in dp83822_phy_reset()
482 return 0; in dp83822_of_init()
487 return 0; in dp83822_of_init()
498 if (val < 0) in dp83822_read_straps()
513 return 0; in dp83822_read_straps()
537 return 0; in dp83822_probe()
549 return 0; in dp83822_suspend()
563 return 0; in dp83822_resume()
610 { DP83822_PHY_ID, 0xfffffff0 },
611 { DP83825I_PHY_ID, 0xfffffff0 },
612 { DP83826C_PHY_ID, 0xfffffff0 },
613 { DP83826NC_PHY_ID, 0xfffffff0 },
614 { DP83825S_PHY_ID, 0xfffffff0 },
615 { DP83825CM_PHY_ID, 0xfffffff0 },
616 { DP83825CS_PHY_ID, 0xfffffff0 },