36 #define MII_LXT970_IER_IEN	0x0002
47 #define MII_LXT971_IER_IEN	0x00f2
65 	if (err < 0)  in lxt970_ack_interrupt()
70 	if (err < 0)  in lxt970_ack_interrupt()
73 	return 0;  in lxt970_ack_interrupt()
81 		return phy_write(phydev, MII_LXT970_IER, 0);  in lxt970_config_intr()
86 	return phy_write(phydev, MII_LXT970_CONFIG, 0);  in lxt970_config_init()
94 	if (err < 0)  in lxt971_ack_interrupt()
97 	return 0;  in lxt971_ack_interrupt()
105 		return phy_write(phydev, MII_LXT971_IER, 0);  in lxt971_config_intr()
122 	if (status < 0)  in lxt973a2_update_link()
126 	if (control < 0)  in lxt973a2_update_link()
132 	} while (status >= 0 && retry-- && status == control);  in lxt973a2_update_link()
134 	if (status < 0)  in lxt973a2_update_link()
137 	if ((status & BMSR_LSTATUS) == 0)  in lxt973a2_update_link()
138 		phydev->link = 0;  in lxt973a2_update_link()
142 	return 0;  in lxt973a2_update_link()
161 		if (adv < 0)  in lxt973a2_read_status()
167 			if (lpa < 0)  in lxt973a2_read_status()
181 		phydev->pause = phydev->asym_pause = 0;  in lxt973a2_read_status()
196 		if (err < 0)  in lxt973a2_read_status()
199 		phydev->pause = phydev->asym_pause = 0;  in lxt973a2_read_status()
203 	return 0;  in lxt973a2_read_status()
225 	return 0;  in lxt973_probe()
231 	return phydev->priv ? 0 : genphy_config_aneg(phydev);  in lxt973_config_aneg()
236 	.phy_id		= 0x78100000,
238 	.phy_id_mask	= 0xfffffff0,
244 	.phy_id		= 0x001378e0,
246 	.phy_id_mask	= 0xfffffff0,
253 	.phy_id		= 0x00137a10,
255 	.phy_id_mask	= 0xffffffff,
257 	.flags		= 0,
264 	.phy_id		= 0x00137a10,
266 	.phy_id_mask	= 0xfffffff0,
268 	.flags		= 0,
278 	{ 0x78100000, 0xfffffff0 },
279 	{ 0x001378e0, 0xfffffff0 },
280 	{ 0x00137a10, 0xfffffff0 },