Lines Matching +full:0 +full:xfffffff0
103 {MSCC_VDDMAC_3300, { 0, 2, 4, 7, 10, 17, 29, 53} },
104 {MSCC_VDDMAC_2500, { 0, 3, 6, 10, 14, 23, 37, 63} },
105 {MSCC_VDDMAC_1800, { 0, 5, 9, 16, 23, 35, 52, 76} },
106 {MSCC_VDDMAC_1500, { 0, 6, 14, 21, 29, 42, 58, 77} },
125 return 0; in vsc85xx_get_sset_count()
138 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_strings()
150 if (val < 0) in vsc85xx_get_stat()
168 for (i = 0; i < priv->nstats; i++) in vsc85xx_get_stats()
199 return 0; in vsc85xx_mdix_get()
221 reg_val = 0; in vsc85xx_mdix_set()
231 if (rc < 0) in vsc85xx_mdix_set()
243 if (reg_val < 0) in vsc85xx_downshift_get()
252 return 0; in vsc85xx_downshift_get()
258 /* Default downshift count 3 (i.e. Bit3:2 = 0b01) */ in vsc85xx_downshift_set()
279 u16 pwd[3] = {0, 0, 0}; in vsc85xx_wol_set()
285 if (rc < 0) { in vsc85xx_wol_set()
292 for (i = 0; i < ARRAY_SIZE(pwd); i++) in vsc85xx_wol_set()
295 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, pwd[0]); in vsc85xx_wol_set()
299 __phy_write(phydev, MSCC_PHY_WOL_LOWER_MAC_ADDR, 0); in vsc85xx_wol_set()
300 __phy_write(phydev, MSCC_PHY_WOL_MID_MAC_ADDR, 0); in vsc85xx_wol_set()
301 __phy_write(phydev, MSCC_PHY_WOL_UPPER_MAC_ADDR, 0); in vsc85xx_wol_set()
305 for (i = 0; i < ARRAY_SIZE(pwd); i++) in vsc85xx_wol_set()
308 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, pwd[0]); in vsc85xx_wol_set()
312 __phy_write(phydev, MSCC_PHY_WOL_LOWER_PASSWD, 0); in vsc85xx_wol_set()
313 __phy_write(phydev, MSCC_PHY_WOL_MID_PASSWD, 0); in vsc85xx_wol_set()
314 __phy_write(phydev, MSCC_PHY_WOL_UPPER_PASSWD, 0); in vsc85xx_wol_set()
324 rc = phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_set()
325 if (rc < 0) in vsc85xx_wol_set()
358 u16 pwd[3] = {0, 0, 0}; in vsc85xx_wol_get()
363 if (rc < 0) in vsc85xx_wol_get()
370 pwd[0] = __phy_read(phydev, MSCC_PHY_WOL_LOWER_PASSWD); in vsc85xx_wol_get()
373 for (i = 0; i < ARRAY_SIZE(pwd); i++) { in vsc85xx_wol_get()
374 wol_conf->sopass[5 - i * 2] = pwd[i] & 0x00ff; in vsc85xx_wol_get()
375 wol_conf->sopass[5 - (i * 2 + 1)] = (pwd[i] & 0xff00) in vsc85xx_wol_get()
381 phy_restore_page(phydev, rc, rc > 0 ? 0 : rc); in vsc85xx_wol_get()
392 u8 sd_array_size = ARRAY_SIZE(edge_table[0].slowdown); in vsc85xx_edge_rate_magic_get()
401 sd = 0; in vsc85xx_edge_rate_magic_get()
403 for (i = 0; i < ARRAY_SIZE(edge_table); i++) in vsc85xx_edge_rate_magic_get()
405 for (j = 0; j < sd_array_size; j++) in vsc85xx_edge_rate_magic_get()
438 return 0; in vsc85xx_edge_rate_magic_get()
456 for (i = 0; i < priv->nleds; i++) { in vsc85xx_dt_led_modes_get()
458 if (ret < 0) in vsc85xx_dt_led_modes_get()
463 if (ret < 0) in vsc85xx_dt_led_modes_get()
468 return 0; in vsc85xx_dt_led_modes_get()
536 u16 reg_val = 0; in vsc85xx_update_rgmii_cntl()
537 u16 mask = 0; in vsc85xx_update_rgmii_cntl()
538 int rc = 0; in vsc85xx_update_rgmii_cntl()
606 __phy_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc85xx_tr_write()
614 {0x0f90, 0x00688980}, in vsc8531_pre_init_seq_set()
615 {0x0696, 0x00000003}, in vsc8531_pre_init_seq_set()
616 {0x07fa, 0x0050100f}, in vsc8531_pre_init_seq_set()
617 {0x1686, 0x00000004}, in vsc8531_pre_init_seq_set()
625 if (rc < 0) in vsc8531_pre_init_seq_set()
628 MSCC_PHY_TEST_PAGE_24, 0, 0x0400); in vsc8531_pre_init_seq_set()
629 if (rc < 0) in vsc8531_pre_init_seq_set()
632 MSCC_PHY_TEST_PAGE_5, 0x0a00, 0x0e00); in vsc8531_pre_init_seq_set()
633 if (rc < 0) in vsc8531_pre_init_seq_set()
637 if (rc < 0) in vsc8531_pre_init_seq_set()
642 if (oldpage < 0) in vsc8531_pre_init_seq_set()
645 for (i = 0; i < ARRAY_SIZE(init_seq); i++) in vsc8531_pre_init_seq_set()
658 {0x0f82, 0x0012b00a}, in vsc85xx_eee_init_seq_set()
659 {0x1686, 0x00000004}, in vsc85xx_eee_init_seq_set()
660 {0x168c, 0x00d2c46f}, in vsc85xx_eee_init_seq_set()
661 {0x17a2, 0x00000620}, in vsc85xx_eee_init_seq_set()
662 {0x16a0, 0x00eeffdd}, in vsc85xx_eee_init_seq_set()
663 {0x16a6, 0x00071448}, in vsc85xx_eee_init_seq_set()
664 {0x16a4, 0x0013132f}, in vsc85xx_eee_init_seq_set()
665 {0x16a8, 0x00000000}, in vsc85xx_eee_init_seq_set()
666 {0x0ffc, 0x00c0a028}, in vsc85xx_eee_init_seq_set()
667 {0x0fe8, 0x0091b06c}, in vsc85xx_eee_init_seq_set()
668 {0x0fea, 0x00041600}, in vsc85xx_eee_init_seq_set()
669 {0x0f80, 0x00000af4}, in vsc85xx_eee_init_seq_set()
670 {0x0fec, 0x00901809}, in vsc85xx_eee_init_seq_set()
671 {0x0fee, 0x0000a6a1}, in vsc85xx_eee_init_seq_set()
672 {0x0ffe, 0x00b01007}, in vsc85xx_eee_init_seq_set()
673 {0x16b0, 0x00eeff00}, in vsc85xx_eee_init_seq_set()
674 {0x16b2, 0x00007000}, in vsc85xx_eee_init_seq_set()
675 {0x16b4, 0x00000814}, in vsc85xx_eee_init_seq_set()
682 if (oldpage < 0) in vsc85xx_eee_init_seq_set()
685 for (i = 0; i < ARRAY_SIZE(init_eee); i++) in vsc85xx_eee_init_seq_set()
728 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 in vsc85xx_csr_read()
729 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. in vsc85xx_csr_read()
736 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) in vsc85xx_csr_read()
738 target &= 0x3; in vsc85xx_csr_read()
740 target = 0; in vsc85xx_csr_read()
757 return 0xffffffff; in vsc85xx_csr_read()
781 * Target_ID[5:2] maps to bits[3:0] of MSCC_EXT_PAGE_CSR_CNTL_20 in vsc85xx_csr_write()
782 * and Target_ID[1:0] maps to bits[13:12] of MSCC_EXT_PAGE_CSR_CNTL_19. in vsc85xx_csr_write()
795 if ((target >> 2 == 0x1) || (target >> 2 == 0x3)) in vsc85xx_csr_write()
797 target &= 0x3; in vsc85xx_csr_write()
799 target = 0; in vsc85xx_csr_write()
821 return 0; in vsc85xx_csr_write()
828 phy_base_write(phydev, MSCC_PHY_TR_LSB, val & GENMASK(15, 0)); in vsc8584_csr_write()
858 return 0; in vsc8584_cmd()
891 return 0; in vsc8584_micro_deassert_reset()
911 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
912 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(4), 0x005b); in vsc8584_micro_assert_reset()
925 PROC_CMD_SGMII_PORT(0) | PROC_CMD_NO_MAC_CONF | in vsc8584_micro_assert_reset()
934 return 0; in vsc8584_micro_assert_reset()
987 phy_base_write(phydev, MSCC_INT_MEM_ADDR, 0x0000); in vsc8584_patch_fw()
989 for (i = 0; i < fw->size; i++) in vsc8584_patch_fw()
998 return 0; in vsc8584_patch_fw()
1011 if (reg != 0x3eb7) { in vsc8574_is_serdes_init()
1017 if (reg != 0x4012) { in vsc8574_is_serdes_init()
1046 {0x0fae, 0x000401bd}, in vsc8574_config_pre_init()
1047 {0x0fac, 0x000f000f}, in vsc8574_config_pre_init()
1048 {0x17a0, 0x00a0f147}, in vsc8574_config_pre_init()
1049 {0x0fe4, 0x00052f54}, in vsc8574_config_pre_init()
1050 {0x1792, 0x0027303d}, in vsc8574_config_pre_init()
1051 {0x07fe, 0x00000704}, in vsc8574_config_pre_init()
1052 {0x0fe0, 0x00060150}, in vsc8574_config_pre_init()
1053 {0x0f82, 0x0012b00a}, in vsc8574_config_pre_init()
1054 {0x0f80, 0x00000d74}, in vsc8574_config_pre_init()
1055 {0x02e0, 0x00000012}, in vsc8574_config_pre_init()
1056 {0x03a2, 0x00050208}, in vsc8574_config_pre_init()
1057 {0x03b2, 0x00009186}, in vsc8574_config_pre_init()
1058 {0x0fb0, 0x000e3700}, in vsc8574_config_pre_init()
1059 {0x1688, 0x00049f81}, in vsc8574_config_pre_init()
1060 {0x0fd2, 0x0000ffff}, in vsc8574_config_pre_init()
1061 {0x168a, 0x00039fa2}, in vsc8574_config_pre_init()
1062 {0x1690, 0x0020640b}, in vsc8574_config_pre_init()
1063 {0x0258, 0x00002220}, in vsc8574_config_pre_init()
1064 {0x025a, 0x00002a20}, in vsc8574_config_pre_init()
1065 {0x025c, 0x00003060}, in vsc8574_config_pre_init()
1066 {0x025e, 0x00003fa0}, in vsc8574_config_pre_init()
1067 {0x03a6, 0x0000e0f0}, in vsc8574_config_pre_init()
1068 {0x0f92, 0x00001489}, in vsc8574_config_pre_init()
1069 {0x16a2, 0x00007000}, in vsc8574_config_pre_init()
1070 {0x16a6, 0x00071448}, in vsc8574_config_pre_init()
1071 {0x16a0, 0x00eeffdd}, in vsc8574_config_pre_init()
1072 {0x0fe8, 0x0091b06c}, in vsc8574_config_pre_init()
1073 {0x0fea, 0x00041600}, in vsc8574_config_pre_init()
1074 {0x16b0, 0x00eeff00}, in vsc8574_config_pre_init()
1075 {0x16b2, 0x00007000}, in vsc8574_config_pre_init()
1076 {0x16b4, 0x00000814}, in vsc8574_config_pre_init()
1077 {0x0f90, 0x00688980}, in vsc8574_config_pre_init()
1078 {0x03a4, 0x0000d8f0}, in vsc8574_config_pre_init()
1079 {0x0fc0, 0x00000400}, in vsc8574_config_pre_init()
1080 {0x07fa, 0x0050100f}, in vsc8574_config_pre_init()
1081 {0x0796, 0x00000003}, in vsc8574_config_pre_init()
1082 {0x07f8, 0x00c3ff98}, in vsc8574_config_pre_init()
1083 {0x0fa4, 0x0018292a}, in vsc8574_config_pre_init()
1084 {0x168c, 0x00d2c46f}, in vsc8574_config_pre_init()
1085 {0x17a2, 0x00000620}, in vsc8574_config_pre_init()
1086 {0x16a4, 0x0013132f}, in vsc8574_config_pre_init()
1087 {0x16a8, 0x00000000}, in vsc8574_config_pre_init()
1088 {0x0ffc, 0x00c0a028}, in vsc8574_config_pre_init()
1089 {0x0fec, 0x00901c09}, in vsc8574_config_pre_init()
1090 {0x0fee, 0x0004a6a1}, in vsc8574_config_pre_init()
1091 {0x0ffe, 0x00b01807}, in vsc8574_config_pre_init()
1094 {0x0486, 0x0008a518}, in vsc8574_config_pre_init()
1095 {0x0488, 0x006dc696}, in vsc8574_config_pre_init()
1096 {0x048a, 0x00000912}, in vsc8574_config_pre_init()
1097 {0x048e, 0x00000db6}, in vsc8574_config_pre_init()
1098 {0x049c, 0x00596596}, in vsc8574_config_pre_init()
1099 {0x049e, 0x00000514}, in vsc8574_config_pre_init()
1100 {0x04a2, 0x00410280}, in vsc8574_config_pre_init()
1101 {0x04a4, 0x00000000}, in vsc8574_config_pre_init()
1102 {0x04a6, 0x00000000}, in vsc8574_config_pre_init()
1103 {0x04a8, 0x00000000}, in vsc8574_config_pre_init()
1104 {0x04aa, 0x00000000}, in vsc8574_config_pre_init()
1105 {0x04ae, 0x007df7dd}, in vsc8574_config_pre_init()
1106 {0x04b0, 0x006d95d4}, in vsc8574_config_pre_init()
1107 {0x04b2, 0x00492410}, in vsc8574_config_pre_init()
1123 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8574_config_pre_init()
1130 phy_base_write(phydev, MSCC_PHY_EXT_PHY_CNTL_2, 0x0040); in vsc8574_config_pre_init()
1134 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_20, 0x4320); in vsc8574_config_pre_init()
1135 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_24, 0x0c00); in vsc8574_config_pre_init()
1136 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_9, 0x18ca); in vsc8574_config_pre_init()
1137 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1b20); in vsc8574_config_pre_init()
1145 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8574_config_pre_init()
1150 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8574_config_pre_init()
1154 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) in vsc8574_config_pre_init()
1210 phy_base_write(phydev, MSCC_TRAP_ROM_ADDR(1), 0x3eb7); in vsc8574_config_pre_init()
1211 phy_base_write(phydev, MSCC_PATCH_RAM_ADDR(1), 0x4012); in vsc8574_config_pre_init()
1261 u32 rd_dat = 0; in vsc8584_mcb_rd_trig()
1265 (0x40000000 | (1L << mcb_slave_num))); in vsc8584_mcb_rd_trig()
1268 !(rd_dat & 0x40000000), in vsc8584_mcb_rd_trig()
1269 4000, 200000, 0, in vsc8584_mcb_rd_trig()
1278 u32 rd_dat = 0; in vsc8584_mcb_wr_trig()
1282 (0x80000000 | (1L << mcb_slave_num))); in vsc8584_mcb_wr_trig()
1285 !(rd_dat & 0x80000000), in vsc8584_mcb_wr_trig()
1286 4000, 200000, 0, in vsc8584_mcb_wr_trig()
1294 int ret = 0; in vsc8584_pll5g_reset()
1296 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1297 if (ret < 0) in vsc8584_pll5g_reset()
1305 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1306 if (ret < 0) in vsc8584_pll5g_reset()
1313 ret = vsc8584_mcb_rd_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1314 if (ret < 0) in vsc8584_pll5g_reset()
1316 dis_fsm = 0; in vsc8584_pll5g_reset()
1322 ret = vsc8584_mcb_wr_trig(phydev, 0x11, 0); in vsc8584_pll5g_reset()
1323 if (ret < 0) in vsc8584_pll5g_reset()
1335 {0x07fa, 0x0050100f}, in vsc8584_config_pre_init()
1336 {0x1688, 0x00049f81}, in vsc8584_config_pre_init()
1337 {0x0f90, 0x00688980}, in vsc8584_config_pre_init()
1338 {0x03a4, 0x0000d8f0}, in vsc8584_config_pre_init()
1339 {0x0fc0, 0x00000400}, in vsc8584_config_pre_init()
1340 {0x0f82, 0x0012b002}, in vsc8584_config_pre_init()
1341 {0x1686, 0x00000004}, in vsc8584_config_pre_init()
1342 {0x168c, 0x00d2c46f}, in vsc8584_config_pre_init()
1343 {0x17a2, 0x00000620}, in vsc8584_config_pre_init()
1344 {0x16a0, 0x00eeffdd}, in vsc8584_config_pre_init()
1345 {0x16a6, 0x00071448}, in vsc8584_config_pre_init()
1346 {0x16a4, 0x0013132f}, in vsc8584_config_pre_init()
1347 {0x16a8, 0x00000000}, in vsc8584_config_pre_init()
1348 {0x0ffc, 0x00c0a028}, in vsc8584_config_pre_init()
1349 {0x0fe8, 0x0091b06c}, in vsc8584_config_pre_init()
1350 {0x0fea, 0x00041600}, in vsc8584_config_pre_init()
1351 {0x0f80, 0x00fffaff}, in vsc8584_config_pre_init()
1352 {0x0fec, 0x00901809}, in vsc8584_config_pre_init()
1353 {0x0ffe, 0x00b01007}, in vsc8584_config_pre_init()
1354 {0x16b0, 0x00eeff00}, in vsc8584_config_pre_init()
1355 {0x16b2, 0x00007000}, in vsc8584_config_pre_init()
1356 {0x16b4, 0x00000814}, in vsc8584_config_pre_init()
1359 {0x0486, 0x0008a518}, in vsc8584_config_pre_init()
1360 {0x0488, 0x006dc696}, in vsc8584_config_pre_init()
1361 {0x048a, 0x00000912}, in vsc8584_config_pre_init()
1376 phy_base_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc8584_config_pre_init()
1389 phy_base_write(phydev, MSCC_PHY_SERDES_TX_CRC_ERR_CNT, 0x2000); in vsc8584_config_pre_init()
1393 phy_base_write(phydev, MSCC_PHY_TEST_PAGE_5, 0x1f20); in vsc8584_config_pre_init()
1401 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x2fa4)); in vsc8584_config_pre_init()
1404 reg &= ~0x007f; in vsc8584_config_pre_init()
1405 reg |= 0x0019; in vsc8584_config_pre_init()
1408 phy_base_write(phydev, MSCC_PHY_TR_CNTL, TR_WRITE | TR_ADDR(0x0fa4)); in vsc8584_config_pre_init()
1410 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8584_config_pre_init()
1415 phy_base_write(phydev, MSCC_PHY_CU_PMD_TX_CNTL, 0x028e); in vsc8584_config_pre_init()
1419 for (i = 0; i < ARRAY_SIZE(pre_init2); i++) in vsc8584_config_pre_init()
1538 * accessed via the PHY whose internal address in the package is 0. in vsc8584_config_init()
1548 * nibble of the phy_id_mask is always 0. This works because in vsc8584_config_init()
1549 * the lowest nibble of the PHY_ID's below are also 0. in vsc8584_config_init()
1551 WARN_ON(phydev->drv->phy_id_mask & 0xf); in vsc8584_config_init()
1663 for (i = 0; i < vsc8531->nleds; i++) { in vsc8584_config_init()
1669 return 0; in vsc8584_config_init()
1682 if (irq_status < 0) in vsc8584_handle_interrupt()
1686 * irq_status would be 0. in vsc8584_handle_interrupt()
1730 for (i = 0; i < vsc8531->nleds; i++) { in vsc85xx_config_init()
1736 return 0; in vsc85xx_config_init()
1741 int rc = 0; in vsc8584_did_interrupt()
1746 return (rc < 0) ? 0 : rc & MII_VSC85XX_INT_MASK_MASK; in vsc8584_did_interrupt()
1756 {0x0f90, 0x00688980}, in vsc8514_config_pre_init()
1757 {0x0786, 0x00000003}, in vsc8514_config_pre_init()
1758 {0x07fa, 0x0050100f}, in vsc8514_config_pre_init()
1759 {0x0f82, 0x0012b002}, in vsc8514_config_pre_init()
1760 {0x1686, 0x00000004}, in vsc8514_config_pre_init()
1761 {0x168c, 0x00d2c46f}, in vsc8514_config_pre_init()
1762 {0x17a2, 0x00000620}, in vsc8514_config_pre_init()
1763 {0x16a0, 0x00eeffdd}, in vsc8514_config_pre_init()
1764 {0x16a6, 0x00071448}, in vsc8514_config_pre_init()
1765 {0x16a4, 0x0013132f}, in vsc8514_config_pre_init()
1766 {0x16a8, 0x00000000}, in vsc8514_config_pre_init()
1767 {0x0ffc, 0x00c0a028}, in vsc8514_config_pre_init()
1768 {0x0fe8, 0x0091b06c}, in vsc8514_config_pre_init()
1769 {0x0fea, 0x00041600}, in vsc8514_config_pre_init()
1770 {0x0f80, 0x00fffaff}, in vsc8514_config_pre_init()
1771 {0x0fec, 0x00901809}, in vsc8514_config_pre_init()
1772 {0x0ffe, 0x00b01007}, in vsc8514_config_pre_init()
1773 {0x16b0, 0x00eeff00}, in vsc8514_config_pre_init()
1774 {0x16b2, 0x00007000}, in vsc8514_config_pre_init()
1775 {0x16b4, 0x00000814}, in vsc8514_config_pre_init()
1783 if (ret < 0) { in vsc8514_config_pre_init()
1803 for (i = 0; i < ARRAY_SIZE(pre_init1); i++) in vsc8514_config_pre_init()
1818 return 0; in vsc8514_config_pre_init()
1838 if (val == 0xffffffff) in __phy_write_mcb_s6g()
1846 return 0; in __phy_write_mcb_s6g()
1913 phy_update_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1915 phy_update_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1918 PHY_S6G_PLL5G_CFG0, 0x7036f145); in vsc8514_config_init()
1922 phy_commit_mcb_s6g(phydev, PHY_S6G_LCPLL_CFG, 0); in vsc8514_config_init()
1928 | (0 << PHY_S6G_PLL_FSM_ENA_POS)); in vsc8514_config_init()
1935 (0 << PHY_S6G_SYS_RST_POS) | in vsc8514_config_init()
1936 (0 << PHY_S6G_ENA_LANE_POS) | in vsc8514_config_init()
1937 (0 << PHY_S6G_ENA_LOOP_POS) | in vsc8514_config_init()
1938 (0 << PHY_S6G_QRATE_POS) | in vsc8514_config_init()
1955 phy_commit_mcb_s6g(phydev, PHY_S6G_DFT_CFG2, 0); in vsc8514_config_init()
1961 0); /* read 6G MCB into CSRs */ in vsc8514_config_init()
1964 if (reg == 0xffffffff) { in vsc8514_config_init()
1978 PHY_S6G_MISC_CFG, 0); in vsc8514_config_init()
1982 phy_commit_mcb_s6g(phydev, PHY_MCB_S6G_CFG, 0); in vsc8514_config_init()
1988 0); /* read 6G MCB into CSRs */ in vsc8514_config_init()
1991 if (reg == 0xffffffff) { in vsc8514_config_init()
2016 for (i = 0; i < vsc8531->nleds; i++) { in vsc8514_config_init()
2031 int rc = 0; in vsc85xx_ack_interrupt()
2036 return (rc < 0) ? rc : 0; in vsc85xx_ack_interrupt()
2050 rc = phy_write(phydev, MII_VSC85XX_INT_MASK, 0); in vsc85xx_config_intr()
2051 if (rc < 0) in vsc85xx_config_intr()
2064 if (rc < 0) in vsc85xx_config_aneg()
2075 if (rc < 0) in vsc85xx_read_status()
2096 vsc8531->base_addr, 0); in vsc8514_probe()
2125 vsc8531->base_addr, 0); in vsc8574_probe()
2192 if (rate_magic < 0) in vsc85xx_probe()
2219 .phy_id_mask = 0xfffffff0,
2243 .phy_id_mask = 0xfffffff0,
2269 .phy_id_mask = 0xfffffff0,
2292 .phy_id_mask = 0xfffffff0,
2316 .phy_id_mask = 0xfffffff0,
2340 .phy_id_mask = 0xfffffff0,
2364 .phy_id_mask = 0xfffffff0,
2388 .phy_id_mask = 0xfffffff0,
2413 .phy_id_mask = 0xfffffff0,
2436 .phy_id_mask = 0xfffffff0,
2463 .phy_id_mask = 0xfffffff0,
2489 .phy_id_mask = 0xfffffff0,
2514 .phy_id_mask = 0xfffffff0,
2539 .phy_id_mask = 0xfffffff0,
2568 { PHY_ID_VSC8502, 0xfffffff0, },
2569 { PHY_ID_VSC8504, 0xfffffff0, },
2570 { PHY_ID_VSC8514, 0xfffffff0, },
2571 { PHY_ID_VSC8530, 0xfffffff0, },
2572 { PHY_ID_VSC8531, 0xfffffff0, },
2573 { PHY_ID_VSC8540, 0xfffffff0, },
2574 { PHY_ID_VSC8541, 0xfffffff0, },
2575 { PHY_ID_VSC8552, 0xfffffff0, },
2576 { PHY_ID_VSC856X, 0xfffffff0, },
2577 { PHY_ID_VSC8572, 0xfffffff0, },
2578 { PHY_ID_VSC8574, 0xfffffff0, },
2579 { PHY_ID_VSC8575, 0xfffffff0, },
2580 { PHY_ID_VSC8582, 0xfffffff0, },
2581 { PHY_ID_VSC8584, 0xfffffff0, },