Lines Matching +full:0 +full:x1c0
25 #define DP83865_PHY_ID 0x20005c7a
27 #define DP83865_INT_STATUS 0x14
28 #define DP83865_INT_MASK 0x15
29 #define DP83865_INT_CLEAR 0x17
31 #define DP83865_INT_REMOTE_FAULT 0x0008
32 #define DP83865_INT_ANE_COMPLETED 0x0010
33 #define DP83865_INT_LINK_CHANGE 0xe000
39 #define NS_EXP_MEM_CTL 0x16
40 #define NS_EXP_MEM_DATA 0x1d
41 #define NS_EXP_MEM_ADD 0x1e
43 #define LED_CTRL_REG 0x13
44 #define AN_FALLBACK_AN 0x0001
45 #define AN_FALLBACK_CRC 0x0002
46 #define AN_FALLBACK_IE 0x0004
50 hdx_loopback_on = 0,
74 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
82 if (ret < 0) in ns_ack_interrupt()
86 * to the corresponding bit in INT_CLEAR (2:0 are reserved) */ in ns_ack_interrupt()
87 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
99 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
100 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
101 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
111 ns_exp_write(phydev, 0x1c0, in ns_10_base_t_hdx_loopack()
112 ns_exp_read(phydev, 0x1c0) | lb_dis); in ns_10_base_t_hdx_loopack()
114 ns_exp_write(phydev, 0x1c0, in ns_10_base_t_hdx_loopack()
115 ns_exp_read(phydev, 0x1c0) & ~lb_dis); in ns_10_base_t_hdx_loopack()
118 (ns_exp_read(phydev, 0x1c0) & lb_dis) ? "off" : "on"); in ns_10_base_t_hdx_loopack()
132 .phy_id_mask = 0xfffffff0,
147 { DP83865_PHY_ID, 0xfffffff0 },