Lines Matching +full:sync +full:- +full:read
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
78 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
93 #define SYNC_ENAB 0 /* Sync Modes Enable */
98 #define MONSYNC 0 /* 8 Bit Sync character */
99 #define BISYNC 0x10 /* 16 bit sync character */
100 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
101 #define EXTSYNC 0x30 /* External Sync Mode */
112 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
139 #define BIT6 1 /* 6 bit/8bit sync */
189 #define SYNCIE 0x10 /* Sync/hunt IE */
195 /* Read Register 0 */
200 #define SYNC_HUNT 0x10 /* Sync/hunt */
205 /* Read Register 1 */
222 /* Read Register 2 (channel b only) - Interrupt vector */
224 /* Read Register 3 (interrupt pending register) ch a only */
232 /* Read Register 8 (receive data register) */
234 /* Read Register 10 (misc status bits) */
240 /* Read Register 12 (lower byte of baud rate generator constant) */
242 /* Read Register 13 (upper byte of baud rate generator constant) */
244 /* Read Register 15 (value of WR 15) */
278 u8 sync; /* Set if in sync mode */ member
294 * Sync DMA
320 u32 rx_overrun; /* Overruns - not done yet */
354 * to read the bps rate the chip has currently
383 #define Z85C30 1 /* CMOS - better */
386 int active; /* Soft interrupt enable - the Mac doesn't
432 * Events are used to schedule things to happen at timer-interrupt