Lines Matching +full:sync +full:- +full:write

1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
25 /* Write Register 0 */
58 /* Write Register 1 */
73 /* Write Register #2 (Interrupt Vector) */
75 /* Write Register 3 */
78 #define	SYNC_L_INH	0x2	/* Sync Character Load Inhibit */
88 /* Write Register 4 */
93 #define	SYNC_ENAB	0	/* Sync Modes Enable */
98 #define	MONSYNC		0	/* 8 Bit Sync character */
99 #define	BISYNC		0x10	/* 16 bit sync character */
100 #define	SDLC		0x20	/* SDLC Mode (01111110 Sync Flag) */
101 #define	EXTSYNC		0x30	/* External Sync Mode */
108 /* Write Register 5 */
112 #define	SDLC_CRC	0x4	/* SDLC/CRC-16 */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
125 /* Write Register 8 (transmit buffer) */
127 /* Write Register 9 (Master interrupt control) */
133 #define	NORESET	0	/* No reset on write to R9 */
138 /* Write Register 10 (misc control bits) */
139 #define	BIT6	1	/* 6 bit/8bit sync */
150 /* Write Register 11 (Clock Mode control) */
166 /* Write Register 12 (lower byte of baud rate generator time constant) */
168 /* Write Register 13 (upper byte of baud rate generator time constant) */
170 /* Write Register 14 (Misc control bits) */
184 /* Write Register 15 (external/status interrupt control) */
189 #define	SYNCIE	0x10	/* Sync/hunt IE */
200 #define	SYNC_HUNT	0x10	/* Sync/hunt */
222 /* Read Register 2 (channel b only) - Interrupt vector */
278 	u8		sync;		/* Set if in sync mode */  member
294 	 *	Sync DMA
320 	u32		rx_overrun;		/* Overruns - not done yet */
383 #define Z85C30	1	/* CMOS - better */
386 	int active;	/* Soft interrupt enable - the Mac doesn't 
432  * Events are used to schedule things to happen at timer-interrupt