Lines Matching +full:tx +full:- +full:output +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
19 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
55 #define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
61 #define TxINT_ENAB 0x2 /* Tx Int Enable */
79 #define ADD_SM 0x4 /* Address Search Mode (SDLC) */
81 #define ENT_HM 0x10 /* Enter Hunt Mode */
100 #define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
101 #define EXTSYNC 0x30 /* External Sync Mode */
103 #define X1CLK 0x0 /* x1 clock mode */
104 #define X16CLK 0x40 /* x16 clock mode */
105 #define X32CLK 0x80 /* x32 clock mode */
106 #define X64CLK 0xC0 /* x64 clock mode */
110 #define TxCRC_ENAB 0x1 /* Tx CRC Enable */
112 #define SDLC_CRC 0x4 /* SDLC/CRC-16 */
113 #define TxENAB 0x8 /* Tx Enable */
115 #define Tx5 0x0 /* Tx 5 bits (or less)/character */
116 #define Tx7 0x20 /* Tx 7 bits/character */
117 #define Tx6 0x40 /* Tx 6 bits/character */
118 #define Tx8 0x60 /* Tx 8 bits/character */
121 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
123 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
140 #define LOOPMODE 2 /* SDLC Loop mode */
144 #define NRZ 0 /* NRZ mode */
145 #define NRZI 0x20 /* NRZI mode */
150 /* Write Register 11 (Clock Mode control) */
151 #define TRxCXT 0 /* TRxC = Xtal output */
153 #define TRxCBR 2 /* TRxC = BR Generator Output */
154 #define TRxCDP 3 /* TRxC = DPLL output */
158 #define TCBR 0x10 /* Transmit clock = BR Generator output */
159 #define TCDPLL 0x18 /* Transmit clock = DPLL output */
162 #define RCBR 0x40 /* Receive clock = BR Generator output */
163 #define RCDPLL 0x60 /* Receive clock = DPLL output */
176 #define SEARCH 0x20 /* Enter search mode */
181 #define SFMM 0xc0 /* Set FM mode */
182 #define SNRZI 0xe0 /* Set NRZI mode */
191 #define TxUIE 0x40 /* Tx Underrun/EOM IE */
198 #define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
202 #define TxEOM 0x40 /* Tx underrun */
222 /* Read Register 2 (channel b only) - Interrupt vector */
226 #define CHBTxIP 0x2 /* Channel B Tx IP */
229 #define CHATxIP 0x10 /* Channel A Tx IP */
256 void (*tx)(struct z8530_channel *); member
278 u8 sync; /* Set if in sync mode */
287 u8 *tx_dma_buf[2]; /* TX flip buffers for DMA */
303 u8 dma_tx; /* TX is to use DMA */
320 u32 rx_overrun; /* Overruns - not done yet */
367 unsigned char tx_stopped; /* output is suspended */
383 #define Z85C30 1 /* CMOS - better */
386 int active; /* Soft interrupt enable - the Mac doesn't
432 * Events are used to schedule things to happen at timer-interrupt