Lines Matching +full:otp +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
12 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
19 #include <linux/nvmem-provider.h>
27 * OTP Bank0 Word0
30 * of two consecutive OTP words.
105 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
107 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
108 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
112 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
122 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
126 * - A write is performed to a shadow register which has been in imx_ocotp_wait_for_busy()
128 * - A read is performed to from a shadow register which has in imx_ocotp_wait_for_busy()
130 * - A program is performed to a fuse word which has been locked in imx_ocotp_wait_for_busy()
131 * - A read is performed to from a fuse word which has been read in imx_ocotp_wait_for_busy()
135 return -EPERM; in imx_ocotp_wait_for_busy()
136 return -ETIMEDOUT; in imx_ocotp_wait_for_busy()
145 void __iomem *base = priv->base; in imx_ocotp_clr_err_if_set()
147 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_clr_err_if_set()
165 index = offset >> 2; in imx_ocotp_read()
166 count = bytes >> 2; in imx_ocotp_read()
168 if (count > (priv->params->nregs - index)) in imx_ocotp_read()
169 count = priv->params->nregs - index; in imx_ocotp_read()
173 ret = clk_prepare_enable(priv->clk); in imx_ocotp_read()
176 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); in imx_ocotp_read()
182 dev_err(priv->dev, "timeout during read setup\n"); in imx_ocotp_read()
187 *buf++ = readl(priv->base + IMX_OCOTP_OFFSET_B0W0 + in imx_ocotp_read()
196 if (*(buf - 1) == IMX_OCOTP_READ_LOCKED_VAL) in imx_ocotp_read()
201 clk_disable_unprepare(priv->clk); in imx_ocotp_read()
215 * ipg_clk. OTP writes will work at maximum bus frequencies as long in imx_ocotp_set_imx6_timing()
218 * Note: there are minimum timings required to ensure an OTP fuse burns in imx_ocotp_set_imx6_timing()
221 * timings given in u-boot we can say: in imx_ocotp_set_imx6_timing()
223 * - Minimum STROBE_PROG time is 10 microseconds. Intuitively 10 in imx_ocotp_set_imx6_timing()
227 * - Minimum STROBE_READ i.e. the time to wait post OTP fuse burn before in imx_ocotp_set_imx6_timing()
230 * - Minimum RELAX timing is 17 nanoseconds. This final RELAX minimum in imx_ocotp_set_imx6_timing()
237 * value will mess up a re-load of the shadow registers post OTP in imx_ocotp_set_imx6_timing()
240 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx6_timing()
242 relax = DIV_ROUND_UP(clk_rate * TIMING_RELAX_NS, 1000000000) - 1; in imx_ocotp_set_imx6_timing()
245 strobe_read += 2 * (relax + 1) - 1; in imx_ocotp_set_imx6_timing()
248 strobe_prog += 2 * (relax + 1) - 1; in imx_ocotp_set_imx6_timing()
250 timing = readl(priv->base + IMX_OCOTP_ADDR_TIMING) & 0x0FC00000; in imx_ocotp_set_imx6_timing()
255 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); in imx_ocotp_set_imx6_timing()
267 clk_rate = clk_get_rate(priv->clk); in imx_ocotp_set_imx7_timing()
276 writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); in imx_ocotp_set_imx7_timing()
290 /* allow only writing one complete OTP word at a time */ in imx_ocotp_write()
291 if ((bytes != priv->config->word_size) || in imx_ocotp_write()
292 (offset % priv->config->word_size)) in imx_ocotp_write()
293 return -EINVAL; in imx_ocotp_write()
297 ret = clk_prepare_enable(priv->clk); in imx_ocotp_write()
300 dev_err(priv->dev, "failed to prepare/enable ocotp clk\n"); in imx_ocotp_write()
305 priv->params->set_timing(priv); in imx_ocotp_write()
307 /* 47.3.1.3.2 in imx_ocotp_write()
315 dev_err(priv->dev, "timeout during timing setup\n"); in imx_ocotp_write()
326 if (priv->params->bank_address_words != 0) { in imx_ocotp_write()
328 * In banked/i.MX7 mode the OTP register bank goes into waddr in imx_ocotp_write()
332 offset = offset / priv->config->word_size; in imx_ocotp_write()
333 waddr = offset / priv->params->bank_address_words; in imx_ocotp_write()
334 word = offset & (priv->params->bank_address_words - 1); in imx_ocotp_write()
337 * Non-banked i.MX6 mode. in imx_ocotp_write()
338 * OTP write/read address specifies one of 128 word address in imx_ocotp_write()
344 ctrl = readl(priv->base + IMX_OCOTP_ADDR_CTRL); in imx_ocotp_write()
345 ctrl &= ~priv->params->ctrl.bm_addr; in imx_ocotp_write()
346 ctrl |= waddr & priv->params->ctrl.bm_addr; in imx_ocotp_write()
349 writel(ctrl, priv->base + IMX_OCOTP_ADDR_CTRL); in imx_ocotp_write()
354 * protect programming same OTP bit twice, before program OCOTP will in imx_ocotp_write()
355 * automatically read fuse value in OTP and use read value to mask in imx_ocotp_write()
357 * a 32-bit word in the OTP per the address in HW_OCOTP_CTRL[ADDR]. Bit in imx_ocotp_write()
358 * fields with 1's will result in that OTP bit being programmed. Bit in imx_ocotp_write()
366 * the OTP serially. During the write operation, HW_OCOTP_DATA cannot be in imx_ocotp_write()
373 if (priv->params->bank_address_words != 0) { in imx_ocotp_write()
377 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
378 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
379 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); in imx_ocotp_write()
380 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
383 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
384 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
385 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); in imx_ocotp_write()
386 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
388 case 2: in imx_ocotp_write()
389 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
390 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
391 writel(0, priv->base + IMX_OCOTP_ADDR_DATA3); in imx_ocotp_write()
392 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
395 writel(0, priv->base + IMX_OCOTP_ADDR_DATA1); in imx_ocotp_write()
396 writel(0, priv->base + IMX_OCOTP_ADDR_DATA2); in imx_ocotp_write()
397 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA3); in imx_ocotp_write()
398 writel(0, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
402 /* Non-banked i.MX6 mode */ in imx_ocotp_write()
403 writel(*buf, priv->base + IMX_OCOTP_ADDR_DATA0); in imx_ocotp_write()
408 * protected or locked region will result in no OTP access and no in imx_ocotp_write()
415 if (ret == -EPERM) { in imx_ocotp_write()
416 dev_err(priv->dev, "failed write to locked region"); in imx_ocotp_write()
419 dev_err(priv->dev, "timeout during data write\n"); in imx_ocotp_write()
426 * OTP during writes, all OTP operations following a write must be in imx_ocotp_write()
427 * separated by 2 us after the clearing of HW_OCOTP_CTRL_BUSY following in imx_ocotp_write()
430 udelay(2); in imx_ocotp_write()
433 writel(priv->params->ctrl.bm_rel_shadows, in imx_ocotp_write()
434 priv->base + IMX_OCOTP_ADDR_CTRL_SET); in imx_ocotp_write()
436 priv->params->ctrl.bm_rel_shadows); in imx_ocotp_write()
438 dev_err(priv->dev, "timeout during shadow register reload\n"); in imx_ocotp_write()
441 clk_disable_unprepare(priv->clk); in imx_ocotp_write()
447 .name = "imx-ocotp",
539 { .compatible = "fsl,imx6q-ocotp", .data = &imx6q_params },
540 { .compatible = "fsl,imx6sl-ocotp", .data = &imx6sl_params },
541 { .compatible = "fsl,imx6sx-ocotp", .data = &imx6sx_params },
542 { .compatible = "fsl,imx6ul-ocotp", .data = &imx6ul_params },
543 { .compatible = "fsl,imx6ull-ocotp", .data = &imx6ull_params },
544 { .compatible = "fsl,imx7d-ocotp", .data = &imx7d_params },
545 { .compatible = "fsl,imx6sll-ocotp", .data = &imx6sll_params },
546 { .compatible = "fsl,imx7ulp-ocotp", .data = &imx7ulp_params },
547 { .compatible = "fsl,imx8mq-ocotp", .data = &imx8mq_params },
548 { .compatible = "fsl,imx8mm-ocotp", .data = &imx8mm_params },
549 { .compatible = "fsl,imx8mn-ocotp", .data = &imx8mn_params },
550 { .compatible = "fsl,imx8mp-ocotp", .data = &imx8mp_params },
557 struct device *dev = &pdev->dev; in imx_ocotp_probe()
563 return -ENOMEM; in imx_ocotp_probe()
565 priv->dev = dev; in imx_ocotp_probe()
567 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_ocotp_probe()
568 if (IS_ERR(priv->base)) in imx_ocotp_probe()
569 return PTR_ERR(priv->base); in imx_ocotp_probe()
571 priv->clk = devm_clk_get(dev, NULL); in imx_ocotp_probe()
572 if (IS_ERR(priv->clk)) in imx_ocotp_probe()
573 return PTR_ERR(priv->clk); in imx_ocotp_probe()
575 priv->params = of_device_get_match_data(&pdev->dev); in imx_ocotp_probe()
576 imx_ocotp_nvmem_config.size = 4 * priv->params->nregs; in imx_ocotp_probe()
579 priv->config = &imx_ocotp_nvmem_config; in imx_ocotp_probe()
581 clk_prepare_enable(priv->clk); in imx_ocotp_probe()
583 clk_disable_unprepare(priv->clk); in imx_ocotp_probe()