Lines Matching +full:pcie +full:- +full:5
1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
58 (GENMASK(7, 5) << ((b) * 8))
60 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
67 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
108 (((aperture) - 2) << ((bar) * 8))
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
132 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
146 /* Region r Outbound PCIe Descriptor Register 0 */
162 /* Region r Outbound PCIe Descriptor Register 1 */
172 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
174 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
180 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
183 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
185 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
201 RP_BAR_UNDEFINED = -1,
214 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
221 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
223 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
263 int (*start_link)(struct cdns_pcie *pcie);
264 void (*stop_link)(struct cdns_pcie *pcie);
265 bool (*link_up)(struct cdns_pcie *pcie);
266 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
270 * struct cdns_pcie - private data for Cadence PCIe controller drivers
273 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
275 * @ops: Platform specific ops to control various inputs from Cadence PCIe
290 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
291 * @pcie: Cadence PCIe controller
292 * @dev: pointer to PCIe device
301 * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
305 struct cdns_pcie pcie; member
316 * struct cdns_pcie_epf - Structure to hold info about endpoint function
324 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
325 * @pcie: Cadence PCIe controller
333 * IRQ) TLP through the PCIe bus.
339 * @lock: spin lock to disable interrupts while modifying PCIe controller
346 struct cdns_pcie pcie; member
363 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) in cdns_pcie_writel() argument
365 writel(value, pcie->reg_base + reg); in cdns_pcie_writel()
368 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_readl() argument
370 return readl(pcie->reg_base + reg); in cdns_pcie_readl()
387 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1); in cdns_pcie_read_sz()
407 mask = ~(((1 << (size * 8)) - 1) << (offset * 8)); in cdns_pcie_write_sz()
414 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, in cdns_pcie_rp_writeb() argument
417 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writeb()
422 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, in cdns_pcie_rp_writew() argument
425 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_writew()
430 static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) in cdns_pcie_rp_readw() argument
432 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; in cdns_pcie_rp_readw()
438 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writeb() argument
441 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writeb()
446 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writew() argument
449 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_writew()
454 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, in cdns_pcie_ep_fn_writel() argument
457 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_writel()
460 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readw() argument
462 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; in cdns_pcie_ep_fn_readw()
467 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) in cdns_pcie_ep_fn_readl() argument
469 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); in cdns_pcie_ep_fn_readl()
472 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie) in cdns_pcie_start_link() argument
474 if (pcie->ops->start_link) in cdns_pcie_start_link()
475 return pcie->ops->start_link(pcie); in cdns_pcie_start_link()
480 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie) in cdns_pcie_stop_link() argument
482 if (pcie->ops->stop_link) in cdns_pcie_stop_link()
483 pcie->ops->stop_link(pcie); in cdns_pcie_stop_link()
486 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie) in cdns_pcie_link_up() argument
488 if (pcie->ops->link_up) in cdns_pcie_link_up()
489 return pcie->ops->link_up(pcie); in cdns_pcie_link_up()
520 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
522 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
526 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
530 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
531 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
532 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
533 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);