Lines Matching +full:perst +full:- +full:regs
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
35 #include "pcie-designware.h"
43 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
96 /* PCIe Port Logic registers (memory-mapped) */
109 /* PHY registers (not memory-mapped) */
146 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_poll_ack()
162 return -ETIMEDOUT; in pcie_phy_poll_ack()
167 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_wait_ack()
187 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
190 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_read()
216 struct dw_pcie *pci = imx6_pcie->pci; in pcie_phy_write()
241 /* wait for ack de-assertion */ in pcie_phy_write()
259 /* wait for ack de-assertion */ in pcie_phy_write()
273 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_pcie_reset_phy()
292 unsigned int fsr, struct pt_regs *regs) in imx6q_pcie_abort_handler() argument
294 unsigned long pc = instruction_pointer(regs); in imx6q_pcie_abort_handler()
300 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
308 val = -1; in imx6q_pcie_abort_handler()
310 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
311 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
316 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
317 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
331 if (dev->pm_domain) in imx6_pcie_attach_pd()
334 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx6_pcie_attach_pd()
335 if (IS_ERR(imx6_pcie->pd_pcie)) in imx6_pcie_attach_pd()
336 return PTR_ERR(imx6_pcie->pd_pcie); in imx6_pcie_attach_pd()
338 if (!imx6_pcie->pd_pcie) in imx6_pcie_attach_pd()
340 link = device_link_add(dev, imx6_pcie->pd_pcie, in imx6_pcie_attach_pd()
346 return -EINVAL; in imx6_pcie_attach_pd()
349 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx6_pcie_attach_pd()
350 if (IS_ERR(imx6_pcie->pd_pcie_phy)) in imx6_pcie_attach_pd()
351 return PTR_ERR(imx6_pcie->pd_pcie_phy); in imx6_pcie_attach_pd()
353 link = device_link_add(dev, imx6_pcie->pd_pcie_phy, in imx6_pcie_attach_pd()
359 return -EINVAL; in imx6_pcie_attach_pd()
367 struct device *dev = imx6_pcie->pci->dev; in imx6_pcie_assert_core_reset()
369 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_assert_core_reset()
372 reset_control_assert(imx6_pcie->pciephy_reset); in imx6_pcie_assert_core_reset()
373 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_assert_core_reset()
376 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_assert_core_reset()
380 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_assert_core_reset()
385 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
390 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_assert_core_reset()
397 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { in imx6_pcie_assert_core_reset()
398 int ret = regulator_disable(imx6_pcie->vpcie); in imx6_pcie_assert_core_reset()
406 if (gpio_is_valid(imx6_pcie->reset_gpio)) in imx6_pcie_assert_core_reset()
407 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_assert_core_reset()
408 imx6_pcie->gpio_active_high); in imx6_pcie_assert_core_reset()
413 WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ); in imx6_pcie_grp_offset()
414 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx6_pcie_grp_offset()
419 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_enable_ref_clk()
420 struct device *dev = pci->dev; in imx6_pcie_enable_ref_clk()
424 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_enable_ref_clk()
426 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi); in imx6_pcie_enable_ref_clk()
432 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_enable_ref_clk()
438 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
447 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_enable_ref_clk()
453 ret = clk_prepare_enable(imx6_pcie->pcie_aux); in imx6_pcie_enable_ref_clk()
464 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
467 regmap_update_bits(imx6_pcie->iomuxc_gpr, offset, in imx6_pcie_enable_ref_clk()
479 struct device *dev = imx6_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
481 if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
491 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_deassert_core_reset()
492 struct device *dev = pci->dev; in imx6_pcie_deassert_core_reset()
495 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) { in imx6_pcie_deassert_core_reset()
496 ret = regulator_enable(imx6_pcie->vpcie); in imx6_pcie_deassert_core_reset()
504 ret = clk_prepare_enable(imx6_pcie->pcie_phy); in imx6_pcie_deassert_core_reset()
510 ret = clk_prepare_enable(imx6_pcie->pcie_bus); in imx6_pcie_deassert_core_reset()
516 ret = clk_prepare_enable(imx6_pcie->pcie); in imx6_pcie_deassert_core_reset()
531 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_deassert_core_reset()
533 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
536 reset_control_deassert(imx6_pcie->pciephy_reset); in imx6_pcie_deassert_core_reset()
538 /* Workaround for ERR010728, failure of PCI-e PLL VCO to in imx6_pcie_deassert_core_reset()
539 * oscillate, especially when cold. This turns off "Duty-cycle in imx6_pcie_deassert_core_reset()
542 if (likely(imx6_pcie->phy_base)) { in imx6_pcie_deassert_core_reset()
543 /* De-assert DCC_FB_EN */ in imx6_pcie_deassert_core_reset()
545 imx6_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx6_pcie_deassert_core_reset()
549 imx6_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx6_pcie_deassert_core_reset()
552 imx6_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx6_pcie_deassert_core_reset()
554 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx6_pcie_deassert_core_reset()
560 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5, in imx6_pcie_deassert_core_reset()
564 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, in imx6_pcie_deassert_core_reset()
574 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_deassert_core_reset()
576 gpio_set_value_cansleep(imx6_pcie->reset_gpio, in imx6_pcie_deassert_core_reset()
577 !imx6_pcie->gpio_active_high); in imx6_pcie_deassert_core_reset()
578 /* Wait for 100ms after PERST# deassertion (PCIe r5.0, 6.6.1) */ in imx6_pcie_deassert_core_reset()
585 clk_disable_unprepare(imx6_pcie->pcie); in imx6_pcie_deassert_core_reset()
587 clk_disable_unprepare(imx6_pcie->pcie_bus); in imx6_pcie_deassert_core_reset()
589 clk_disable_unprepare(imx6_pcie->pcie_phy); in imx6_pcie_deassert_core_reset()
591 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) { in imx6_pcie_deassert_core_reset()
592 ret = regulator_disable(imx6_pcie->vpcie); in imx6_pcie_deassert_core_reset()
603 if (imx6_pcie->drvdata->variant == IMX8MQ && in imx6_pcie_configure_type()
604 imx6_pcie->controller_id == 1) { in imx6_pcie_configure_type()
614 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val); in imx6_pcie_configure_type()
619 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_init_phy()
625 regmap_update_bits(imx6_pcie->iomuxc_gpr, in imx6_pcie_init_phy()
631 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
635 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
640 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
644 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_init_phy()
647 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
649 imx6_pcie->tx_deemph_gen1 << 0); in imx6_pcie_init_phy()
650 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
652 imx6_pcie->tx_deemph_gen2_3p5db << 6); in imx6_pcie_init_phy()
653 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
655 imx6_pcie->tx_deemph_gen2_6db << 12); in imx6_pcie_init_phy()
656 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
658 imx6_pcie->tx_swing_full << 18); in imx6_pcie_init_phy()
659 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx6_pcie_init_phy()
661 imx6_pcie->tx_swing_low << 25); in imx6_pcie_init_phy()
670 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy); in imx6_setup_phy_mpll()
674 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY)) in imx6_setup_phy_mpll()
693 dev_err(imx6_pcie->pci->dev, in imx6_setup_phy_mpll()
695 return -EINVAL; in imx6_setup_phy_mpll()
717 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_wait_for_speed_change()
718 struct device *dev = pci->dev; in imx6_pcie_wait_for_speed_change()
731 return -ETIMEDOUT; in imx6_pcie_wait_for_speed_change()
738 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_enable()
742 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_enable()
748 reset_control_deassert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_enable()
755 struct dw_pcie *pci = imx6_pcie->pci; in imx6_pcie_establish_link()
756 struct device *dev = pci->dev; in imx6_pcie_establish_link()
778 if (pci->link_gen == 2) { in imx6_pcie_establish_link()
793 if (imx6_pcie->drvdata->flags & in imx6_pcie_establish_link()
798 * occurs and we go Gen1 -> yep, Gen1. The difference in imx6_pcie_establish_link()
856 struct dw_pcie *pci = imx6_pcie->pci; in imx6_add_pcie_port()
857 struct pcie_port *pp = &pci->pp; in imx6_add_pcie_port()
858 struct device *dev = &pdev->dev; in imx6_add_pcie_port()
862 pp->msi_irq = platform_get_irq_byname(pdev, "msi"); in imx6_add_pcie_port()
863 if (pp->msi_irq < 0) in imx6_add_pcie_port()
864 return pp->msi_irq; in imx6_add_pcie_port()
867 pp->ops = &imx6_pcie_host_ops; in imx6_add_pcie_port()
879 /* No special ops needed, but pcie-designware still expects this struct */
887 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_ltssm_disable()
890 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_ltssm_disable()
894 reset_control_assert(imx6_pcie->apps_reset); in imx6_pcie_ltssm_disable()
903 struct device *dev = imx6_pcie->pci->dev; in imx6_pcie_pm_turnoff()
906 if (imx6_pcie->turnoff_reset) { in imx6_pcie_pm_turnoff()
907 reset_control_assert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
908 reset_control_deassert(imx6_pcie->turnoff_reset); in imx6_pcie_pm_turnoff()
913 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_pm_turnoff()
915 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
918 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_pm_turnoff()
930 * The standard recommends a 1-10ms timeout after which to in imx6_pcie_pm_turnoff()
939 clk_disable_unprepare(imx6_pcie->pcie); in imx6_pcie_clk_disable()
940 clk_disable_unprepare(imx6_pcie->pcie_phy); in imx6_pcie_clk_disable()
941 clk_disable_unprepare(imx6_pcie->pcie_bus); in imx6_pcie_clk_disable()
943 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_clk_disable()
945 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi); in imx6_pcie_clk_disable()
948 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6_pcie_clk_disable()
953 clk_disable_unprepare(imx6_pcie->pcie_aux); in imx6_pcie_clk_disable()
964 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_suspend_noirq()
978 struct pcie_port *pp = &imx6_pcie->pci->pp; in imx6_pcie_resume_noirq()
980 if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx6_pcie_resume_noirq()
1003 struct device *dev = &pdev->dev; in imx6_pcie_probe()
1008 struct device_node *node = dev->of_node; in imx6_pcie_probe()
1014 return -ENOMEM; in imx6_pcie_probe()
1018 return -ENOMEM; in imx6_pcie_probe()
1020 pci->dev = dev; in imx6_pcie_probe()
1021 pci->ops = &dw_pcie_ops; in imx6_pcie_probe()
1023 imx6_pcie->pci = pci; in imx6_pcie_probe()
1024 imx6_pcie->drvdata = of_device_get_match_data(dev); in imx6_pcie_probe()
1027 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx6_pcie_probe()
1036 imx6_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx6_pcie_probe()
1037 if (IS_ERR(imx6_pcie->phy_base)) { in imx6_pcie_probe()
1039 return PTR_ERR(imx6_pcie->phy_base); in imx6_pcie_probe()
1044 pci->dbi_base = devm_ioremap_resource(dev, dbi_base); in imx6_pcie_probe()
1045 if (IS_ERR(pci->dbi_base)) in imx6_pcie_probe()
1046 return PTR_ERR(pci->dbi_base); in imx6_pcie_probe()
1049 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); in imx6_pcie_probe()
1050 imx6_pcie->gpio_active_high = of_property_read_bool(node, in imx6_pcie_probe()
1051 "reset-gpio-active-high"); in imx6_pcie_probe()
1052 if (gpio_is_valid(imx6_pcie->reset_gpio)) { in imx6_pcie_probe()
1053 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio, in imx6_pcie_probe()
1054 imx6_pcie->gpio_active_high ? in imx6_pcie_probe()
1062 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) { in imx6_pcie_probe()
1063 return imx6_pcie->reset_gpio; in imx6_pcie_probe()
1067 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy"); in imx6_pcie_probe()
1068 if (IS_ERR(imx6_pcie->pcie_phy)) in imx6_pcie_probe()
1069 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy), in imx6_pcie_probe()
1072 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus"); in imx6_pcie_probe()
1073 if (IS_ERR(imx6_pcie->pcie_bus)) in imx6_pcie_probe()
1074 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus), in imx6_pcie_probe()
1077 imx6_pcie->pcie = devm_clk_get(dev, "pcie"); in imx6_pcie_probe()
1078 if (IS_ERR(imx6_pcie->pcie)) in imx6_pcie_probe()
1079 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie), in imx6_pcie_probe()
1082 switch (imx6_pcie->drvdata->variant) { in imx6_pcie_probe()
1084 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev, in imx6_pcie_probe()
1086 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) in imx6_pcie_probe()
1087 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi), in imx6_pcie_probe()
1091 imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux"); in imx6_pcie_probe()
1092 if (IS_ERR(imx6_pcie->pcie_aux)) in imx6_pcie_probe()
1093 return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux), in imx6_pcie_probe()
1097 if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR) in imx6_pcie_probe()
1098 imx6_pcie->controller_id = 1; in imx6_pcie_probe()
1100 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1102 if (IS_ERR(imx6_pcie->pciephy_reset)) { in imx6_pcie_probe()
1104 return PTR_ERR(imx6_pcie->pciephy_reset); in imx6_pcie_probe()
1107 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev, in imx6_pcie_probe()
1109 if (IS_ERR(imx6_pcie->apps_reset)) { in imx6_pcie_probe()
1111 return PTR_ERR(imx6_pcie->apps_reset); in imx6_pcie_probe()
1119 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff"); in imx6_pcie_probe()
1120 if (IS_ERR(imx6_pcie->turnoff_reset)) { in imx6_pcie_probe()
1122 return PTR_ERR(imx6_pcie->turnoff_reset); in imx6_pcie_probe()
1126 imx6_pcie->iomuxc_gpr = in imx6_pcie_probe()
1127 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); in imx6_pcie_probe()
1128 if (IS_ERR(imx6_pcie->iomuxc_gpr)) { in imx6_pcie_probe()
1130 return PTR_ERR(imx6_pcie->iomuxc_gpr); in imx6_pcie_probe()
1134 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx6_pcie_probe()
1135 &imx6_pcie->tx_deemph_gen1)) in imx6_pcie_probe()
1136 imx6_pcie->tx_deemph_gen1 = 0; in imx6_pcie_probe()
1138 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx6_pcie_probe()
1139 &imx6_pcie->tx_deemph_gen2_3p5db)) in imx6_pcie_probe()
1140 imx6_pcie->tx_deemph_gen2_3p5db = 0; in imx6_pcie_probe()
1142 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx6_pcie_probe()
1143 &imx6_pcie->tx_deemph_gen2_6db)) in imx6_pcie_probe()
1144 imx6_pcie->tx_deemph_gen2_6db = 20; in imx6_pcie_probe()
1146 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx6_pcie_probe()
1147 &imx6_pcie->tx_swing_full)) in imx6_pcie_probe()
1148 imx6_pcie->tx_swing_full = 127; in imx6_pcie_probe()
1150 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx6_pcie_probe()
1151 &imx6_pcie->tx_swing_low)) in imx6_pcie_probe()
1152 imx6_pcie->tx_swing_low = 127; in imx6_pcie_probe()
1155 pci->link_gen = 1; in imx6_pcie_probe()
1156 ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen); in imx6_pcie_probe()
1158 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx6_pcie_probe()
1159 if (IS_ERR(imx6_pcie->vpcie)) { in imx6_pcie_probe()
1160 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV) in imx6_pcie_probe()
1161 return PTR_ERR(imx6_pcie->vpcie); in imx6_pcie_probe()
1162 imx6_pcie->vpcie = NULL; in imx6_pcie_probe()
1221 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1222 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1223 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1224 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1225 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1231 .name = "imx6q-pcie",
1243 struct pci_bus *bus = dev->bus; in imx6_pcie_quirk()
1244 struct pcie_port *pp = bus->sysdata; in imx6_pcie_quirk()
1247 if (!bus->dev.parent || !bus->dev.parent->parent) in imx6_pcie_quirk()
1251 if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver) in imx6_pcie_quirk()
1262 if (imx6_pcie->drvdata->dbi_length) { in imx6_pcie_quirk()
1263 dev->cfg_size = imx6_pcie->drvdata->dbi_length; in imx6_pcie_quirk()
1264 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx6_pcie_quirk()
1265 dev->cfg_size); in imx6_pcie_quirk()
1279 return -ENODEV; in imx6_pcie_init()
1285 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx6_pcie_init()
1290 "external abort on non-linefetch"); in imx6_pcie_init()