Lines Matching +full:pci +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/phy/phy.h>
17 #include "../../pci.h"
18 #include "pcie-designware.h"
20 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
68 struct dw_pcie pci; member
74 struct phy *phy; member
90 return readl(lpp->app_base + ofs); in pcie_app_rd()
95 writel(val, lpp->app_base + ofs); in pcie_app_wr()
101 pcie_update_bits(lpp->app_base, ofs, mask, val); in pcie_app_wr_mask()
106 return dw_pcie_readl_dbi(&lpp->pci, ofs); in pcie_rc_cfg_rd()
111 dw_pcie_writel_dbi(&lpp->pci, ofs, val); in pcie_rc_cfg_wr()
117 pcie_update_bits(lpp->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
134 u8 offset = dw_pcie_find_capability(&lpp->pci, PCI_CAP_ID_EXP); in intel_pcie_link_setup()
142 static void intel_pcie_init_n_fts(struct dw_pcie *pci) in intel_pcie_init_n_fts() argument
144 switch (pci->link_gen) { in intel_pcie_init_n_fts()
146 pci->n_fts[1] = PORT_AFR_N_FTS_GEN3; in intel_pcie_init_n_fts()
149 pci->n_fts[1] = PORT_AFR_N_FTS_GEN4; in intel_pcie_init_n_fts()
152 pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT; in intel_pcie_init_n_fts()
155 pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT; in intel_pcie_init_n_fts()
162 intel_pcie_init_n_fts(&lpp->pci); in intel_pcie_rc_setup()
163 dw_pcie_setup_rc(&lpp->pci.pp); in intel_pcie_rc_setup()
164 dw_pcie_upconfig_setup(&lpp->pci); in intel_pcie_rc_setup()
169 struct device *dev = lpp->pci.dev; in intel_pcie_ep_rst_init()
172 lpp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); in intel_pcie_ep_rst_init()
173 if (IS_ERR(lpp->reset_gpio)) { in intel_pcie_ep_rst_init()
174 ret = PTR_ERR(lpp->reset_gpio); in intel_pcie_ep_rst_init()
175 if (ret != -EPROBE_DEFER) in intel_pcie_ep_rst_init()
188 reset_control_assert(lpp->core_rst); in intel_pcie_core_rst_assert()
194 * One micro-second delay to make sure the reset pulse in intel_pcie_core_rst_deassert()
198 reset_control_deassert(lpp->core_rst); in intel_pcie_core_rst_deassert()
201 * Some SoC core reset also reset PHY, more delay needed in intel_pcie_core_rst_deassert()
209 gpiod_set_value_cansleep(lpp->reset_gpio, 1); in intel_pcie_device_rst_assert()
214 msleep(lpp->rst_intrvl); in intel_pcie_device_rst_deassert()
215 gpiod_set_value_cansleep(lpp->reset_gpio, 0); in intel_pcie_device_rst_deassert()
223 return dw_pcie_wait_for_link(&lpp->pci); in intel_pcie_app_logic_setup()
235 struct dw_pcie *pci = &lpp->pci; in intel_pcie_get_resources() local
236 struct device *dev = pci->dev; in intel_pcie_get_resources()
239 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi"); in intel_pcie_get_resources()
240 if (IS_ERR(pci->dbi_base)) in intel_pcie_get_resources()
241 return PTR_ERR(pci->dbi_base); in intel_pcie_get_resources()
243 lpp->core_clk = devm_clk_get(dev, NULL); in intel_pcie_get_resources()
244 if (IS_ERR(lpp->core_clk)) { in intel_pcie_get_resources()
245 ret = PTR_ERR(lpp->core_clk); in intel_pcie_get_resources()
246 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
251 lpp->core_rst = devm_reset_control_get(dev, NULL); in intel_pcie_get_resources()
252 if (IS_ERR(lpp->core_rst)) { in intel_pcie_get_resources()
253 ret = PTR_ERR(lpp->core_rst); in intel_pcie_get_resources()
254 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
259 ret = device_property_read_u32(dev, "reset-assert-ms", in intel_pcie_get_resources()
260 &lpp->rst_intrvl); in intel_pcie_get_resources()
262 lpp->rst_intrvl = RESET_INTERVAL_MS; in intel_pcie_get_resources()
264 lpp->app_base = devm_platform_ioremap_resource_byname(pdev, "app"); in intel_pcie_get_resources()
265 if (IS_ERR(lpp->app_base)) in intel_pcie_get_resources()
266 return PTR_ERR(lpp->app_base); in intel_pcie_get_resources()
268 lpp->phy = devm_phy_get(dev, "pcie"); in intel_pcie_get_resources()
269 if (IS_ERR(lpp->phy)) { in intel_pcie_get_resources()
270 ret = PTR_ERR(lpp->phy); in intel_pcie_get_resources()
271 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
272 dev_err(dev, "Couldn't get pcie-phy: %d\n", ret); in intel_pcie_get_resources()
281 phy_exit(lpp->phy); in intel_pcie_deinit_phy()
288 struct dw_pcie *pci = &lpp->pci; in intel_pcie_wait_l2() local
290 if (pci->link_gen < 3) in intel_pcie_wait_l2()
298 ret = readl_poll_timeout(lpp->app_base + PCIE_APP_PMC, value, in intel_pcie_wait_l2()
302 dev_err(lpp->pci.dev, "PCIe link enter L2 timeout!\n"); in intel_pcie_wait_l2()
309 if (dw_pcie_link_up(&lpp->pci)) in intel_pcie_turn_off()
324 ret = phy_init(lpp->phy); in intel_pcie_host_setup()
330 ret = clk_prepare_enable(lpp->core_clk); in intel_pcie_host_setup()
332 dev_err(lpp->pci.dev, "Core clock enable failed: %d\n", ret); in intel_pcie_host_setup()
348 clk_disable_unprepare(lpp->core_clk); in intel_pcie_host_setup()
360 clk_disable_unprepare(lpp->core_clk); in __intel_pcie_remove()
368 struct pcie_port *pp = &lpp->pci.pp; in intel_pcie_remove()
387 clk_disable_unprepare(lpp->core_clk); in intel_pcie_suspend_noirq()
400 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in intel_pcie_rc_init() local
401 struct intel_pcie_port *lpp = dev_get_drvdata(pci->dev); in intel_pcie_rc_init()
437 struct device *dev = &pdev->dev; in intel_pcie_probe()
440 struct dw_pcie *pci; in intel_pcie_probe() local
445 return -ENOMEM; in intel_pcie_probe()
448 pci = &lpp->pci; in intel_pcie_probe()
449 pci->dev = dev; in intel_pcie_probe()
450 pp = &pci->pp; in intel_pcie_probe()
462 return -ENODEV; in intel_pcie_probe()
464 pci->ops = &intel_pcie_ops; in intel_pcie_probe()
465 pci->version = data->pcie_ver; in intel_pcie_probe()
466 pci->atu_base = pci->dbi_base + data->pcie_atu_offset; in intel_pcie_probe()
467 pp->ops = &intel_pcie_dw_ops; in intel_pcie_probe()
479 pci->num_viewport = data->num_viewport; in intel_pcie_probe()
490 { .compatible = "intel,lgm-pcie", .data = &pcie_data },
498 .name = "intel-gw-pcie",