Lines Matching +full:supports +full:- +full:clkreq
1 // SPDX-License-Identifier: GPL-2.0+
34 #include "pcie-designware.h"
36 #include <soc/tegra/bpmp-abi.h>
324 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
329 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
344 * NOTE:- Since this scenario is uncommon and link as such is not in apply_bad_link_workaround()
346 * transitioning to Gen-2 speed in apply_bad_link_workaround()
348 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
351 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
352 dev_warn(pci->dev, "PCIe link is bad, width reduced\n"); in apply_bad_link_workaround()
353 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
357 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
360 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
363 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
372 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_rp_irq_handler()
373 struct pcie_port *pp = &pci->pp; in tegra_pcie_rp_irq_handler()
410 val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in tegra_pcie_rp_irq_handler()
412 dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w & in tegra_pcie_rp_irq_handler()
421 dev_info(pci->dev, "CDM check complete\n"); in tegra_pcie_rp_irq_handler()
425 dev_err(pci->dev, "CDM comparison mismatch\n"); in tegra_pcie_rp_irq_handler()
429 dev_err(pci->dev, "CDM Logic error\n"); in tegra_pcie_rp_irq_handler()
434 dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", val); in tegra_pcie_rp_irq_handler()
469 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_ep_irq_thread()
472 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_ep_irq_thread()
478 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_ep_irq_thread()
481 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in tegra_pcie_ep_irq_thread()
490 /* 110us for both snoop and no-snoop */ in tegra_pcie_ep_irq_thread()
510 dev_err(pcie->dev, "Failed to send LTR message\n"); in tegra_pcie_ep_irq_thread()
519 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_hard_irq()
534 dev_dbg(pcie->dev, "Link is up with Host\n"); in tegra_pcie_ep_hard_irq()
553 dev_warn(pcie->dev, "Random interrupt (STATUS = 0x%08X)\n", in tegra_pcie_ep_hard_irq()
567 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_rd_own_conf()
584 * when it is accessed with link being in ASPM-L1 state. in tegra_pcie_dw_wr_own_conf()
604 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l11()
606 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l11()
613 val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub); in disable_aspm_l12()
615 dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val); in disable_aspm_l12()
622 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]); in event_counter_prog()
627 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); in event_counter_prog()
628 val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]); in event_counter_prog()
636 dev_get_drvdata(s->private); in aspm_state_cnt()
655 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], in aspm_state_cnt()
658 /* Re-enable counting */ in aspm_state_cnt()
661 dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val); in aspm_state_cnt()
668 struct dw_pcie *pci = &pcie->pci; in init_host_aspm()
672 pcie->cfg_link_cap_l1sub = val + PCI_L1SS_CAP; in init_host_aspm()
677 dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val); in init_host_aspm()
680 val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub); in init_host_aspm()
682 val |= (pcie->aspm_cmrt << 8); in init_host_aspm()
683 val |= (pcie->aspm_pwr_on_t << 19); in init_host_aspm()
684 dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val); in init_host_aspm()
689 val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT); in init_host_aspm()
696 debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt", pcie->debugfs, in init_debugfs()
721 if (pcie->enable_cdm_check) { in tegra_pcie_enable_system_interrupts()
732 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
734 pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w); in tegra_pcie_enable_system_interrupts()
736 val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base + in tegra_pcie_enable_system_interrupts()
739 dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL, in tegra_pcie_enable_system_interrupts()
809 struct dw_pcie *pci = &pcie->pci; in config_gen3_gen4_eq_presets()
813 for (i = 0; i < pcie->num_lanes; i++) { in config_gen3_gen4_eq_presets()
885 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP); in tegra_pcie_prepare_host()
887 val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes); in tegra_pcie_prepare_host()
888 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val); in tegra_pcie_prepare_host()
898 if (pcie->update_fc_fixup) { in tegra_pcie_prepare_host()
906 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in tegra_pcie_prepare_host()
920 /* De-assert RST */ in tegra_pcie_prepare_host()
934 pp->bridge->ops = &tegra_pci_ops; in tegra_pcie_dw_host_init()
957 dev_info(pci->dev, "Link is down in DLL"); in tegra_pcie_dw_host_init()
958 dev_info(pci->dev, "Trying again with DLFE disabled\n"); in tegra_pcie_dw_host_init()
964 reset_control_assert(pcie->core_rst); in tegra_pcie_dw_host_init()
965 reset_control_deassert(pcie->core_rst); in tegra_pcie_dw_host_init()
978 speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) & in tegra_pcie_dw_host_init()
984 clk_set_rate(pcie->core_clk, pcie_gen_freq[speed]); in tegra_pcie_dw_host_init()
994 u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_dw_link_up()
1001 pp->num_vectors = MAX_MSI_IRQS; in tegra_pcie_set_msi_vec_num()
1008 enable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_start_link()
1017 disable_irq(pcie->pex_rst_irq); in tegra_pcie_dw_stop_link()
1033 unsigned int phy_count = pcie->phy_count; in tegra_pcie_disable_phy()
1035 while (phy_count--) { in tegra_pcie_disable_phy()
1036 phy_power_off(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1037 phy_exit(pcie->phys[phy_count]); in tegra_pcie_disable_phy()
1046 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_enable_phy()
1047 ret = phy_init(pcie->phys[i]); in tegra_pcie_enable_phy()
1051 ret = phy_power_on(pcie->phys[i]); in tegra_pcie_enable_phy()
1059 while (i--) { in tegra_pcie_enable_phy()
1060 phy_power_off(pcie->phys[i]); in tegra_pcie_enable_phy()
1062 phy_exit(pcie->phys[i]); in tegra_pcie_enable_phy()
1070 struct device_node *np = pcie->dev->of_node; in tegra_pcie_dw_parse_dt()
1073 ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt); in tegra_pcie_dw_parse_dt()
1075 dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret); in tegra_pcie_dw_parse_dt()
1079 ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us", in tegra_pcie_dw_parse_dt()
1080 &pcie->aspm_pwr_on_t); in tegra_pcie_dw_parse_dt()
1082 dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n", in tegra_pcie_dw_parse_dt()
1085 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1086 &pcie->aspm_l0s_enter_lat); in tegra_pcie_dw_parse_dt()
1088 dev_info(pcie->dev, in tegra_pcie_dw_parse_dt()
1091 ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes); in tegra_pcie_dw_parse_dt()
1093 dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret); in tegra_pcie_dw_parse_dt()
1097 ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid); in tegra_pcie_dw_parse_dt()
1099 dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret); in tegra_pcie_dw_parse_dt()
1103 ret = of_property_count_strings(np, "phy-names"); in tegra_pcie_dw_parse_dt()
1105 dev_err(pcie->dev, "Failed to find PHY entries: %d\n", in tegra_pcie_dw_parse_dt()
1109 pcie->phy_count = ret; in tegra_pcie_dw_parse_dt()
1111 if (of_property_read_bool(np, "nvidia,update-fc-fixup")) in tegra_pcie_dw_parse_dt()
1112 pcie->update_fc_fixup = true; in tegra_pcie_dw_parse_dt()
1114 pcie->supports_clkreq = in tegra_pcie_dw_parse_dt()
1115 of_property_read_bool(pcie->dev->of_node, "supports-clkreq"); in tegra_pcie_dw_parse_dt()
1117 pcie->enable_cdm_check = in tegra_pcie_dw_parse_dt()
1118 of_property_read_bool(np, "snps,enable-cdm-check"); in tegra_pcie_dw_parse_dt()
1120 if (pcie->mode == DW_PCIE_RC_TYPE) in tegra_pcie_dw_parse_dt()
1124 pcie->pex_rst_gpiod = devm_gpiod_get(pcie->dev, "reset", GPIOD_IN); in tegra_pcie_dw_parse_dt()
1125 if (IS_ERR(pcie->pex_rst_gpiod)) { in tegra_pcie_dw_parse_dt()
1126 int err = PTR_ERR(pcie->pex_rst_gpiod); in tegra_pcie_dw_parse_dt()
1129 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1132 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1138 pcie->pex_refclk_sel_gpiod = devm_gpiod_get(pcie->dev, in tegra_pcie_dw_parse_dt()
1139 "nvidia,refclk-select", in tegra_pcie_dw_parse_dt()
1141 if (IS_ERR(pcie->pex_refclk_sel_gpiod)) { in tegra_pcie_dw_parse_dt()
1142 int err = PTR_ERR(pcie->pex_refclk_sel_gpiod); in tegra_pcie_dw_parse_dt()
1145 if (err == -EPROBE_DEFER) in tegra_pcie_dw_parse_dt()
1148 dev_printk(level, pcie->dev, in tegra_pcie_dw_parse_dt()
1151 pcie->pex_refclk_sel_gpiod = NULL; in tegra_pcie_dw_parse_dt()
1164 /* Controller-5 doesn't need to have its state set by BPMP-FW */ in tegra_pcie_bpmp_set_ctrl_state()
1165 if (pcie->cid == 5) in tegra_pcie_bpmp_set_ctrl_state()
1172 req.controller_state.pcie_controller = pcie->cid; in tegra_pcie_bpmp_set_ctrl_state()
1182 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_ctrl_state()
1197 req.ep_ctrlr_pll_init.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1200 req.ep_ctrlr_pll_off.ep_controller = pcie->cid; in tegra_pcie_bpmp_set_pll_state()
1210 return tegra_bpmp_transfer(pcie->bpmp, &msg); in tegra_pcie_bpmp_set_pll_state()
1215 struct pcie_port *pp = &pcie->pci.pp; in tegra_pcie_downstream_dev_to_D0()
1224 * This is as per PCI Express Base r4.0 v1.0 September 27-2017, in tegra_pcie_downstream_dev_to_D0()
1228 list_for_each_entry(child, &pp->bridge->bus->children, node) { in tegra_pcie_downstream_dev_to_D0()
1230 if (child->parent == pp->bridge->bus) { in tegra_pcie_downstream_dev_to_D0()
1237 dev_err(pcie->dev, "Failed to find downstream devices\n"); in tegra_pcie_downstream_dev_to_D0()
1241 list_for_each_entry(pdev, &root_bus->devices, bus_list) { in tegra_pcie_downstream_dev_to_D0()
1242 if (PCI_SLOT(pdev->devfn) == 0) { in tegra_pcie_downstream_dev_to_D0()
1244 dev_err(pcie->dev, in tegra_pcie_downstream_dev_to_D0()
1246 dev_name(&pdev->dev)); in tegra_pcie_downstream_dev_to_D0()
1253 pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3"); in tegra_pcie_get_slot_regulators()
1254 if (IS_ERR(pcie->slot_ctl_3v3)) { in tegra_pcie_get_slot_regulators()
1255 if (PTR_ERR(pcie->slot_ctl_3v3) != -ENODEV) in tegra_pcie_get_slot_regulators()
1256 return PTR_ERR(pcie->slot_ctl_3v3); in tegra_pcie_get_slot_regulators()
1258 pcie->slot_ctl_3v3 = NULL; in tegra_pcie_get_slot_regulators()
1261 pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v"); in tegra_pcie_get_slot_regulators()
1262 if (IS_ERR(pcie->slot_ctl_12v)) { in tegra_pcie_get_slot_regulators()
1263 if (PTR_ERR(pcie->slot_ctl_12v) != -ENODEV) in tegra_pcie_get_slot_regulators()
1264 return PTR_ERR(pcie->slot_ctl_12v); in tegra_pcie_get_slot_regulators()
1266 pcie->slot_ctl_12v = NULL; in tegra_pcie_get_slot_regulators()
1276 if (pcie->slot_ctl_3v3) { in tegra_pcie_enable_slot_regulators()
1277 ret = regulator_enable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1279 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1285 if (pcie->slot_ctl_12v) { in tegra_pcie_enable_slot_regulators()
1286 ret = regulator_enable(pcie->slot_ctl_12v); in tegra_pcie_enable_slot_regulators()
1288 dev_err(pcie->dev, in tegra_pcie_enable_slot_regulators()
1296 * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive) in tegra_pcie_enable_slot_regulators()
1299 if (pcie->slot_ctl_3v3 || pcie->slot_ctl_12v) in tegra_pcie_enable_slot_regulators()
1305 if (pcie->slot_ctl_3v3) in tegra_pcie_enable_slot_regulators()
1306 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_enable_slot_regulators()
1312 if (pcie->slot_ctl_12v) in tegra_pcie_disable_slot_regulators()
1313 regulator_disable(pcie->slot_ctl_12v); in tegra_pcie_disable_slot_regulators()
1314 if (pcie->slot_ctl_3v3) in tegra_pcie_disable_slot_regulators()
1315 regulator_disable(pcie->slot_ctl_3v3); in tegra_pcie_disable_slot_regulators()
1326 dev_err(pcie->dev, in tegra_pcie_config_controller()
1327 "Failed to enable controller %u: %d\n", pcie->cid, ret); in tegra_pcie_config_controller()
1335 ret = regulator_enable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1337 dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret); in tegra_pcie_config_controller()
1341 ret = clk_prepare_enable(pcie->core_clk); in tegra_pcie_config_controller()
1343 dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret); in tegra_pcie_config_controller()
1347 ret = reset_control_deassert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1349 dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n", in tegra_pcie_config_controller()
1365 dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret); in tegra_pcie_config_controller()
1370 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1385 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1394 pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK, in tegra_pcie_config_controller()
1397 reset_control_deassert(pcie->core_rst); in tegra_pcie_config_controller()
1399 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in tegra_pcie_config_controller()
1402 /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */ in tegra_pcie_config_controller()
1403 if (!pcie->supports_clkreq) { in tegra_pcie_config_controller()
1411 reset_control_assert(pcie->core_apb_rst); in tegra_pcie_config_controller()
1413 clk_disable_unprepare(pcie->core_clk); in tegra_pcie_config_controller()
1415 regulator_disable(pcie->pex_ctl_supply); in tegra_pcie_config_controller()
1428 ret = reset_control_assert(pcie->core_rst); in __deinit_controller()
1430 dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n", in __deinit_controller()
1437 ret = reset_control_assert(pcie->core_apb_rst); in __deinit_controller()
1439 dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret); in __deinit_controller()
1443 clk_disable_unprepare(pcie->core_clk); in __deinit_controller()
1445 ret = regulator_disable(pcie->pex_ctl_supply); in __deinit_controller()
1447 dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret); in __deinit_controller()
1455 dev_err(pcie->dev, "Failed to disable controller %d: %d\n", in __deinit_controller()
1456 pcie->cid, ret); in __deinit_controller()
1465 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_init_controller()
1466 struct pcie_port *pp = &pci->pp; in tegra_pcie_init_controller()
1473 pp->ops = &tegra_pcie_dw_host_ops; in tegra_pcie_init_controller()
1477 dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret); in tegra_pcie_init_controller()
1491 if (!tegra_pcie_dw_link_up(&pcie->pci)) in tegra_pcie_try_link_l2()
1498 return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val, in tegra_pcie_try_link_l2()
1508 if (!tegra_pcie_dw_link_up(&pcie->pci)) { in tegra_pcie_dw_pme_turnoff()
1509 dev_dbg(pcie->dev, "PCIe link is not up...!\n"); in tegra_pcie_dw_pme_turnoff()
1514 dev_info(pcie->dev, "Link didn't transition to L2 state\n"); in tegra_pcie_dw_pme_turnoff()
1525 err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, in tegra_pcie_dw_pme_turnoff()
1533 dev_info(pcie->dev, "Link didn't go to detect state\n"); in tegra_pcie_dw_pme_turnoff()
1542 * DBI registers may not be accessible after this as PLL-E would be in tegra_pcie_dw_pme_turnoff()
1543 * down depending on how CLKREQ is pulled by end point in tegra_pcie_dw_pme_turnoff()
1556 dw_pcie_host_deinit(&pcie->pci.pp); in tegra_pcie_deinit_controller()
1564 struct pcie_port *pp = &pcie->pci.pp; in tegra_pcie_config_rp()
1565 struct device *dev = pcie->dev; in tegra_pcie_config_rp()
1570 pp->msi_irq = of_irq_get_byname(dev->of_node, "msi"); in tegra_pcie_config_rp()
1571 if (!pp->msi_irq) { in tegra_pcie_config_rp()
1573 return -ENODEV; in tegra_pcie_config_rp()
1594 pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci); in tegra_pcie_config_rp()
1595 if (!pcie->link_state) { in tegra_pcie_config_rp()
1596 ret = -ENOMEDIUM; in tegra_pcie_config_rp()
1600 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); in tegra_pcie_config_rp()
1602 ret = -ENOMEM; in tegra_pcie_config_rp()
1606 pcie->debugfs = debugfs_create_dir(name, NULL); in tegra_pcie_config_rp()
1624 if (pcie->ep_state == EP_STATE_DISABLED) in pex_ep_event_pex_rst_assert()
1632 ret = readl_poll_timeout(pcie->appl_base + APPL_DEBUG, val, in pex_ep_event_pex_rst_assert()
1638 dev_err(pcie->dev, "Failed to go Detect state: %d\n", ret); in pex_ep_event_pex_rst_assert()
1640 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_assert()
1644 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_assert()
1646 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_assert()
1648 pm_runtime_put_sync(pcie->dev); in pex_ep_event_pex_rst_assert()
1652 dev_err(pcie->dev, "Failed to turn off UPHY: %d\n", ret); in pex_ep_event_pex_rst_assert()
1654 pcie->ep_state = EP_STATE_DISABLED; in pex_ep_event_pex_rst_assert()
1655 dev_dbg(pcie->dev, "Uninitialization of endpoint is completed\n"); in pex_ep_event_pex_rst_assert()
1660 struct dw_pcie *pci = &pcie->pci; in pex_ep_event_pex_rst_deassert()
1661 struct dw_pcie_ep *ep = &pci->ep; in pex_ep_event_pex_rst_deassert()
1662 struct device *dev = pcie->dev; in pex_ep_event_pex_rst_deassert()
1666 if (pcie->ep_state == EP_STATE_ENABLED) in pex_ep_event_pex_rst_deassert()
1682 ret = clk_prepare_enable(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1688 ret = reset_control_deassert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1740 appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK, in pex_ep_event_pex_rst_deassert()
1743 appl_writel(pcie, pcie->atu_dma_res->start & in pex_ep_event_pex_rst_deassert()
1758 reset_control_deassert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1760 if (pcie->update_fc_fixup) { in pex_ep_event_pex_rst_deassert()
1770 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */ in pex_ep_event_pex_rst_deassert()
1771 if (!pcie->supports_clkreq) { in pex_ep_event_pex_rst_deassert()
1780 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, in pex_ep_event_pex_rst_deassert()
1782 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); in pex_ep_event_pex_rst_deassert()
1784 val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1787 val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK); in pex_ep_event_pex_rst_deassert()
1803 pcie->ep_state = EP_STATE_ENABLED; in pex_ep_event_pex_rst_deassert()
1809 reset_control_assert(pcie->core_rst); in pex_ep_event_pex_rst_deassert()
1812 reset_control_assert(pcie->core_apb_rst); in pex_ep_event_pex_rst_deassert()
1814 clk_disable_unprepare(pcie->core_clk); in pex_ep_event_pex_rst_deassert()
1825 if (gpiod_get_value(pcie->pex_rst_gpiod)) in tegra_pcie_ep_pex_rst_irq()
1835 /* Tegra194 supports only INTA */ in tegra_pcie_ep_raise_legacy_irq()
1837 return -EINVAL; in tegra_pcie_ep_raise_legacy_irq()
1848 return -EINVAL; in tegra_pcie_ep_raise_msi_irq()
1857 struct dw_pcie_ep *ep = &pcie->pci.ep; in tegra_pcie_ep_raise_msix_irq()
1859 writel(irq, ep->msi_mem); in tegra_pcie_ep_raise_msix_irq()
1882 dev_err(pci->dev, "Unknown IRQ type\n"); in tegra_pcie_ep_raise_irq()
1883 return -EPERM; in tegra_pcie_ep_raise_irq()
1913 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_config_ep()
1914 struct device *dev = pcie->dev; in tegra_pcie_config_ep()
1920 ep = &pci->ep; in tegra_pcie_config_ep()
1921 ep->ops = &pcie_ep_ops; in tegra_pcie_config_ep()
1925 return -EINVAL; in tegra_pcie_config_ep()
1927 ep->phys_base = res->start; in tegra_pcie_config_ep()
1928 ep->addr_size = resource_size(res); in tegra_pcie_config_ep()
1929 ep->page_size = SZ_64K; in tegra_pcie_config_ep()
1931 ret = gpiod_set_debounce(pcie->pex_rst_gpiod, PERST_DEBOUNCE_TIME); in tegra_pcie_config_ep()
1938 ret = gpiod_to_irq(pcie->pex_rst_gpiod); in tegra_pcie_config_ep()
1943 pcie->pex_rst_irq = (unsigned int)ret; in tegra_pcie_config_ep()
1946 pcie->cid); in tegra_pcie_config_ep()
1949 return -ENOMEM; in tegra_pcie_config_ep()
1952 irq_set_status_flags(pcie->pex_rst_irq, IRQ_NOAUTOEN); in tegra_pcie_config_ep()
1954 pcie->ep_state = EP_STATE_DISABLED; in tegra_pcie_config_ep()
1956 ret = devm_request_threaded_irq(dev, pcie->pex_rst_irq, NULL, in tegra_pcie_config_ep()
1967 pcie->cid); in tegra_pcie_config_ep()
1970 return -ENOMEM; in tegra_pcie_config_ep()
1989 struct device *dev = &pdev->dev; in tegra_pcie_dw_probe()
2004 return -ENOMEM; in tegra_pcie_dw_probe()
2006 pci = &pcie->pci; in tegra_pcie_dw_probe()
2007 pci->dev = &pdev->dev; in tegra_pcie_dw_probe()
2008 pci->ops = &tegra_dw_pcie_ops; in tegra_pcie_dw_probe()
2009 pci->n_fts[0] = N_FTS_VAL; in tegra_pcie_dw_probe()
2010 pci->n_fts[1] = FTS_VAL; in tegra_pcie_dw_probe()
2012 pp = &pci->pp; in tegra_pcie_dw_probe()
2013 pcie->dev = &pdev->dev; in tegra_pcie_dw_probe()
2014 pcie->mode = (enum dw_pcie_device_mode)data->mode; in tegra_pcie_dw_probe()
2020 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2033 if (ret == -EPROBE_DEFER) in tegra_pcie_dw_probe()
2042 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_probe()
2043 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1); in tegra_pcie_dw_probe()
2045 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl"); in tegra_pcie_dw_probe()
2046 if (IS_ERR(pcie->pex_ctl_supply)) { in tegra_pcie_dw_probe()
2047 ret = PTR_ERR(pcie->pex_ctl_supply); in tegra_pcie_dw_probe()
2048 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2050 PTR_ERR(pcie->pex_ctl_supply)); in tegra_pcie_dw_probe()
2054 pcie->core_clk = devm_clk_get(dev, "core"); in tegra_pcie_dw_probe()
2055 if (IS_ERR(pcie->core_clk)) { in tegra_pcie_dw_probe()
2057 PTR_ERR(pcie->core_clk)); in tegra_pcie_dw_probe()
2058 return PTR_ERR(pcie->core_clk); in tegra_pcie_dw_probe()
2061 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, in tegra_pcie_dw_probe()
2063 if (!pcie->appl_res) { in tegra_pcie_dw_probe()
2065 return -ENODEV; in tegra_pcie_dw_probe()
2068 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res); in tegra_pcie_dw_probe()
2069 if (IS_ERR(pcie->appl_base)) in tegra_pcie_dw_probe()
2070 return PTR_ERR(pcie->appl_base); in tegra_pcie_dw_probe()
2072 pcie->core_apb_rst = devm_reset_control_get(dev, "apb"); in tegra_pcie_dw_probe()
2073 if (IS_ERR(pcie->core_apb_rst)) { in tegra_pcie_dw_probe()
2075 PTR_ERR(pcie->core_apb_rst)); in tegra_pcie_dw_probe()
2076 return PTR_ERR(pcie->core_apb_rst); in tegra_pcie_dw_probe()
2079 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL); in tegra_pcie_dw_probe()
2081 return -ENOMEM; in tegra_pcie_dw_probe()
2083 for (i = 0; i < pcie->phy_count; i++) { in tegra_pcie_dw_probe()
2084 name = kasprintf(GFP_KERNEL, "p2u-%u", i); in tegra_pcie_dw_probe()
2087 return -ENOMEM; in tegra_pcie_dw_probe()
2093 if (ret != -EPROBE_DEFER) in tegra_pcie_dw_probe()
2099 pcie->phys = phys; in tegra_pcie_dw_probe()
2104 return -ENODEV; in tegra_pcie_dw_probe()
2106 pcie->dbi_res = dbi_res; in tegra_pcie_dw_probe()
2108 pci->dbi_base = devm_ioremap_resource(dev, dbi_res); in tegra_pcie_dw_probe()
2109 if (IS_ERR(pci->dbi_base)) in tegra_pcie_dw_probe()
2110 return PTR_ERR(pci->dbi_base); in tegra_pcie_dw_probe()
2113 pci->dbi_base2 = pci->dbi_base + 0x1000; in tegra_pcie_dw_probe()
2119 return -ENODEV; in tegra_pcie_dw_probe()
2121 pcie->atu_dma_res = atu_dma_res; in tegra_pcie_dw_probe()
2123 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res); in tegra_pcie_dw_probe()
2124 if (IS_ERR(pci->atu_base)) in tegra_pcie_dw_probe()
2125 return PTR_ERR(pci->atu_base); in tegra_pcie_dw_probe()
2127 pcie->core_rst = devm_reset_control_get(dev, "core"); in tegra_pcie_dw_probe()
2128 if (IS_ERR(pcie->core_rst)) { in tegra_pcie_dw_probe()
2130 PTR_ERR(pcie->core_rst)); in tegra_pcie_dw_probe()
2131 return PTR_ERR(pcie->core_rst); in tegra_pcie_dw_probe()
2134 pp->irq = platform_get_irq_byname(pdev, "intr"); in tegra_pcie_dw_probe()
2135 if (pp->irq < 0) in tegra_pcie_dw_probe()
2136 return pp->irq; in tegra_pcie_dw_probe()
2138 pcie->bpmp = tegra_bpmp_get(dev); in tegra_pcie_dw_probe()
2139 if (IS_ERR(pcie->bpmp)) in tegra_pcie_dw_probe()
2140 return PTR_ERR(pcie->bpmp); in tegra_pcie_dw_probe()
2144 switch (pcie->mode) { in tegra_pcie_dw_probe()
2146 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler, in tegra_pcie_dw_probe()
2147 IRQF_SHARED, "tegra-pcie-intr", pcie); in tegra_pcie_dw_probe()
2149 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2155 if (ret && ret != -ENOMEDIUM) in tegra_pcie_dw_probe()
2162 ret = devm_request_threaded_irq(dev, pp->irq, in tegra_pcie_dw_probe()
2166 "tegra-pcie-ep-intr", pcie); in tegra_pcie_dw_probe()
2168 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, in tegra_pcie_dw_probe()
2179 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode); in tegra_pcie_dw_probe()
2183 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_probe()
2191 if (!pcie->link_state) in tegra_pcie_dw_remove()
2194 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_remove()
2196 pm_runtime_put_sync(pcie->dev); in tegra_pcie_dw_remove()
2197 pm_runtime_disable(pcie->dev); in tegra_pcie_dw_remove()
2198 tegra_bpmp_put(pcie->bpmp); in tegra_pcie_dw_remove()
2199 if (pcie->pex_refclk_sel_gpiod) in tegra_pcie_dw_remove()
2200 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 0); in tegra_pcie_dw_remove()
2210 if (!pcie->link_state) in tegra_pcie_dw_suspend_late()
2227 if (!pcie->link_state) in tegra_pcie_dw_suspend_noirq()
2231 pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci, in tegra_pcie_dw_suspend_noirq()
2244 if (!pcie->link_state) in tegra_pcie_dw_resume_noirq()
2251 ret = tegra_pcie_dw_host_init(&pcie->pci.pp); in tegra_pcie_dw_resume_noirq()
2258 dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN, in tegra_pcie_dw_resume_noirq()
2259 pcie->msi_ctrl_int); in tegra_pcie_dw_resume_noirq()
2272 if (!pcie->link_state) in tegra_pcie_dw_resume_early()
2291 if (!pcie->link_state) in tegra_pcie_dw_shutdown()
2294 debugfs_remove_recursive(pcie->debugfs); in tegra_pcie_dw_shutdown()
2297 disable_irq(pcie->pci.pp.irq); in tegra_pcie_dw_shutdown()
2299 disable_irq(pcie->pci.pp.msi_irq); in tegra_pcie_dw_shutdown()
2315 .compatible = "nvidia,tegra194-pcie",
2319 .compatible = "nvidia,tegra194-pcie-ep",
2337 .name = "tegra194-pcie",