Lines Matching +full:pcie +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Mobiveil PCIe Host controller
6 * Copyright 2019-2020 NXP
28 #include "pcie-mobiveil.h"
40 if ((bus->primary == to_pci_host_bridge(bus->bridge)->busnr) && (PCI_SLOT(devfn) > 0)) in mobiveil_pcie_valid_device()
47 * mobiveil_pcie_map_bus - routine to get the configuration base of either
53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
70 value = bus->number << PAB_BUS_SHIFT | in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
76 return rp->config_axi_slave_base + where; in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
91 struct mobiveil_msi *msi = &rp->msi; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
106 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
111 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
117 virq = irq_find_mapping(rp->intx_domain, in mobiveil_pcie_isr()
118 bit + 1); in mobiveil_pcie_isr()
126 mobiveil_csr_writel(pcie, in mobiveil_pcie_isr()
127 1 << (PAB_INTX_START + bit), in mobiveil_pcie_isr()
131 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
139 msi_status = readl_relaxed(pcie->apb_csr_base + MSI_STATUS_OFFSET); in mobiveil_pcie_isr()
142 while (msi_status & 1) { in mobiveil_pcie_isr()
143 msi_data = readl_relaxed(pcie->apb_csr_base + MSI_DATA_OFFSET); in mobiveil_pcie_isr()
151 msi_addr_lo = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
153 msi_addr_hi = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
158 virq = irq_find_mapping(msi->dev_domain, msi_data); in mobiveil_pcie_isr()
162 msi_status = readl_relaxed(pcie->apb_csr_base + in mobiveil_pcie_isr()
167 mobiveil_csr_writel(pcie, intr_status, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
171 static int mobiveil_pcie_parse_dt(struct mobiveil_pcie *pcie) in mobiveil_pcie_parse_dt() argument
173 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_parse_dt()
174 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_parse_dt()
175 struct device_node *node = dev->of_node; in mobiveil_pcie_parse_dt()
176 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_parse_dt()
182 rp->config_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
183 if (IS_ERR(rp->config_axi_slave_base)) in mobiveil_pcie_parse_dt()
184 return PTR_ERR(rp->config_axi_slave_base); in mobiveil_pcie_parse_dt()
185 rp->ob_io_res = res; in mobiveil_pcie_parse_dt()
190 pcie->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_parse_dt()
191 if (IS_ERR(pcie->csr_axi_slave_base)) in mobiveil_pcie_parse_dt()
192 return PTR_ERR(pcie->csr_axi_slave_base); in mobiveil_pcie_parse_dt()
193 pcie->pcie_reg_base = res->start; in mobiveil_pcie_parse_dt()
196 if (of_property_read_u32(node, "apio-wins", &pcie->apio_wins)) in mobiveil_pcie_parse_dt()
197 pcie->apio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
199 if (of_property_read_u32(node, "ppio-wins", &pcie->ppio_wins)) in mobiveil_pcie_parse_dt()
200 pcie->ppio_wins = MAX_PIO_WINDOWS; in mobiveil_pcie_parse_dt()
205 static void mobiveil_pcie_enable_msi(struct mobiveil_pcie *pcie) in mobiveil_pcie_enable_msi() argument
207 phys_addr_t msg_addr = pcie->pcie_reg_base; in mobiveil_pcie_enable_msi()
208 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_pcie_enable_msi()
210 msi->num_of_vectors = PCI_NUM_MSI; in mobiveil_pcie_enable_msi()
211 msi->msi_pages_phys = (phys_addr_t)msg_addr; in mobiveil_pcie_enable_msi()
214 pcie->apb_csr_base + MSI_BASE_LO_OFFSET); in mobiveil_pcie_enable_msi()
216 pcie->apb_csr_base + MSI_BASE_HI_OFFSET); in mobiveil_pcie_enable_msi()
217 writel_relaxed(4096, pcie->apb_csr_base + MSI_SIZE_OFFSET); in mobiveil_pcie_enable_msi()
218 writel_relaxed(1, pcie->apb_csr_base + MSI_ENABLE_OFFSET); in mobiveil_pcie_enable_msi()
221 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit) in mobiveil_host_init() argument
223 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_host_init()
224 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_host_init()
228 pcie->ib_wins_configured = 0; in mobiveil_host_init()
229 pcie->ob_wins_configured = 0; in mobiveil_host_init()
233 value = mobiveil_csr_readl(pcie, PCI_PRIMARY_BUS); in mobiveil_host_init()
236 mobiveil_csr_writel(pcie, value, PCI_PRIMARY_BUS); in mobiveil_host_init()
243 value = mobiveil_csr_readl(pcie, PCI_COMMAND); in mobiveil_host_init()
245 mobiveil_csr_writel(pcie, value, PCI_COMMAND); in mobiveil_host_init()
248 * program PIO Enable Bit to 1 (and PEX PIO Enable to 1) in PAB_CTRL in mobiveil_host_init()
251 pab_ctrl = mobiveil_csr_readl(pcie, PAB_CTRL); in mobiveil_host_init()
252 pab_ctrl |= (1 << AMBA_PIO_ENABLE_SHIFT) | (1 << PEX_PIO_ENABLE_SHIFT); in mobiveil_host_init()
253 mobiveil_csr_writel(pcie, pab_ctrl, PAB_CTRL); in mobiveil_host_init()
256 * program PIO Enable Bit to 1 and Config Window Enable Bit to 1 in in mobiveil_host_init()
259 value = mobiveil_csr_readl(pcie, PAB_AXI_PIO_CTRL); in mobiveil_host_init()
261 mobiveil_csr_writel(pcie, value, PAB_AXI_PIO_CTRL); in mobiveil_host_init()
263 /* Enable PCIe PIO master */ in mobiveil_host_init()
264 value = mobiveil_csr_readl(pcie, PAB_PEX_PIO_CTRL); in mobiveil_host_init()
265 value |= 1 << PIO_ENABLE_SHIFT; in mobiveil_host_init()
266 mobiveil_csr_writel(pcie, value, PAB_PEX_PIO_CTRL); in mobiveil_host_init()
276 program_ob_windows(pcie, WIN_NUM_0, rp->ob_io_res->start, 0, in mobiveil_host_init()
277 CFG_WINDOW_TYPE, resource_size(rp->ob_io_res)); in mobiveil_host_init()
280 program_ib_windows(pcie, WIN_NUM_0, 0, 0, MEM_WINDOW_TYPE, IB_WIN_SIZE); in mobiveil_host_init()
283 resource_list_for_each_entry(win, &bridge->windows) { in mobiveil_host_init()
284 if (resource_type(win->res) == IORESOURCE_MEM) in mobiveil_host_init()
286 else if (resource_type(win->res) == IORESOURCE_IO) in mobiveil_host_init()
292 program_ob_windows(pcie, pcie->ob_wins_configured, in mobiveil_host_init()
293 win->res->start, in mobiveil_host_init()
294 win->res->start - win->offset, in mobiveil_host_init()
295 type, resource_size(win->res)); in mobiveil_host_init()
298 /* fixup for PCIe class register */ in mobiveil_host_init()
299 value = mobiveil_csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS); in mobiveil_host_init()
302 mobiveil_csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS); in mobiveil_host_init()
309 struct irq_desc *desc = irq_to_desc(data->irq); in mobiveil_mask_intx_irq()
310 struct mobiveil_pcie *pcie; in mobiveil_mask_intx_irq() local
315 pcie = irq_desc_get_chip_data(desc); in mobiveil_mask_intx_irq()
316 rp = &pcie->rp; in mobiveil_mask_intx_irq()
317 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_mask_intx_irq()
318 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
319 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_mask_intx_irq()
321 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); in mobiveil_mask_intx_irq()
322 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_mask_intx_irq()
327 struct irq_desc *desc = irq_to_desc(data->irq); in mobiveil_unmask_intx_irq()
328 struct mobiveil_pcie *pcie; in mobiveil_unmask_intx_irq() local
333 pcie = irq_desc_get_chip_data(desc); in mobiveil_unmask_intx_irq()
334 rp = &pcie->rp; in mobiveil_unmask_intx_irq()
335 mask = 1 << ((data->hwirq + PAB_INTX_START) - 1); in mobiveil_unmask_intx_irq()
336 raw_spin_lock_irqsave(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
337 shifted_val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_unmask_intx_irq()
339 mobiveil_csr_writel(pcie, shifted_val, PAB_INTP_AMBA_MISC_ENB); in mobiveil_unmask_intx_irq()
340 raw_spin_unlock_irqrestore(&rp->intx_mask_lock, flags); in mobiveil_unmask_intx_irq()
356 irq_set_chip_data(irq, domain->host_data); in mobiveil_pcie_intx_map()
367 .name = "Mobiveil PCIe MSI",
380 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(data); in mobiveil_compose_msi_msg() local
381 phys_addr_t addr = pcie->pcie_reg_base + (data->hwirq * sizeof(int)); in mobiveil_compose_msi_msg()
383 msg->address_lo = lower_32_bits(addr); in mobiveil_compose_msi_msg()
384 msg->address_hi = upper_32_bits(addr); in mobiveil_compose_msi_msg()
385 msg->data = data->hwirq; in mobiveil_compose_msi_msg()
387 dev_dbg(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n", in mobiveil_compose_msi_msg()
388 (int)data->hwirq, msg->address_hi, msg->address_lo); in mobiveil_compose_msi_msg()
394 return -EINVAL; in mobiveil_msi_set_affinity()
407 struct mobiveil_pcie *pcie = domain->host_data; in mobiveil_irq_msi_domain_alloc() local
408 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_alloc()
411 WARN_ON(nr_irqs != 1); in mobiveil_irq_msi_domain_alloc()
412 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
414 bit = find_first_zero_bit(msi->msi_irq_in_use, msi->num_of_vectors); in mobiveil_irq_msi_domain_alloc()
415 if (bit >= msi->num_of_vectors) { in mobiveil_irq_msi_domain_alloc()
416 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
417 return -ENOSPC; in mobiveil_irq_msi_domain_alloc()
420 set_bit(bit, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_alloc()
422 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_alloc()
425 domain->host_data, handle_level_irq, NULL, NULL); in mobiveil_irq_msi_domain_alloc()
434 struct mobiveil_pcie *pcie = irq_data_get_irq_chip_data(d); in mobiveil_irq_msi_domain_free() local
435 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_irq_msi_domain_free()
437 mutex_lock(&msi->lock); in mobiveil_irq_msi_domain_free()
439 if (!test_bit(d->hwirq, msi->msi_irq_in_use)) in mobiveil_irq_msi_domain_free()
440 dev_err(&pcie->pdev->dev, "trying to free unused MSI#%lu\n", in mobiveil_irq_msi_domain_free()
441 d->hwirq); in mobiveil_irq_msi_domain_free()
443 __clear_bit(d->hwirq, msi->msi_irq_in_use); in mobiveil_irq_msi_domain_free()
445 mutex_unlock(&msi->lock); in mobiveil_irq_msi_domain_free()
452 static int mobiveil_allocate_msi_domains(struct mobiveil_pcie *pcie) in mobiveil_allocate_msi_domains() argument
454 struct device *dev = &pcie->pdev->dev; in mobiveil_allocate_msi_domains()
455 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in mobiveil_allocate_msi_domains()
456 struct mobiveil_msi *msi = &pcie->rp.msi; in mobiveil_allocate_msi_domains()
458 mutex_init(&msi->lock); in mobiveil_allocate_msi_domains()
459 msi->dev_domain = irq_domain_add_linear(NULL, msi->num_of_vectors, in mobiveil_allocate_msi_domains()
460 &msi_domain_ops, pcie); in mobiveil_allocate_msi_domains()
461 if (!msi->dev_domain) { in mobiveil_allocate_msi_domains()
463 return -ENOMEM; in mobiveil_allocate_msi_domains()
466 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in mobiveil_allocate_msi_domains()
468 msi->dev_domain); in mobiveil_allocate_msi_domains()
469 if (!msi->msi_domain) { in mobiveil_allocate_msi_domains()
471 irq_domain_remove(msi->dev_domain); in mobiveil_allocate_msi_domains()
472 return -ENOMEM; in mobiveil_allocate_msi_domains()
478 static int mobiveil_pcie_init_irq_domain(struct mobiveil_pcie *pcie) in mobiveil_pcie_init_irq_domain() argument
480 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_init_irq_domain()
481 struct device_node *node = dev->of_node; in mobiveil_pcie_init_irq_domain()
482 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_init_irq_domain()
485 rp->intx_domain = irq_domain_add_linear(node, PCI_NUM_INTX, in mobiveil_pcie_init_irq_domain()
486 &intx_domain_ops, pcie); in mobiveil_pcie_init_irq_domain()
488 if (!rp->intx_domain) { in mobiveil_pcie_init_irq_domain()
490 return -ENOMEM; in mobiveil_pcie_init_irq_domain()
493 raw_spin_lock_init(&rp->intx_mask_lock); in mobiveil_pcie_init_irq_domain()
496 return mobiveil_allocate_msi_domains(pcie); in mobiveil_pcie_init_irq_domain()
499 static int mobiveil_pcie_integrated_interrupt_init(struct mobiveil_pcie *pcie) in mobiveil_pcie_integrated_interrupt_init() argument
501 struct platform_device *pdev = pcie->pdev; in mobiveil_pcie_integrated_interrupt_init()
502 struct device *dev = &pdev->dev; in mobiveil_pcie_integrated_interrupt_init()
503 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_integrated_interrupt_init()
509 pcie->apb_csr_base = devm_pci_remap_cfg_resource(dev, res); in mobiveil_pcie_integrated_interrupt_init()
510 if (IS_ERR(pcie->apb_csr_base)) in mobiveil_pcie_integrated_interrupt_init()
511 return PTR_ERR(pcie->apb_csr_base); in mobiveil_pcie_integrated_interrupt_init()
514 mobiveil_pcie_enable_msi(pcie); in mobiveil_pcie_integrated_interrupt_init()
516 rp->irq = platform_get_irq(pdev, 0); in mobiveil_pcie_integrated_interrupt_init()
517 if (rp->irq < 0) in mobiveil_pcie_integrated_interrupt_init()
518 return rp->irq; in mobiveil_pcie_integrated_interrupt_init()
521 ret = mobiveil_pcie_init_irq_domain(pcie); in mobiveil_pcie_integrated_interrupt_init()
527 irq_set_chained_handler_and_data(rp->irq, mobiveil_pcie_isr, pcie); in mobiveil_pcie_integrated_interrupt_init()
530 mobiveil_csr_writel(pcie, (PAB_INTP_INTX_MASK | PAB_INTP_MSI_MASK), in mobiveil_pcie_integrated_interrupt_init()
537 static int mobiveil_pcie_interrupt_init(struct mobiveil_pcie *pcie) in mobiveil_pcie_interrupt_init() argument
539 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_interrupt_init()
541 if (rp->ops->interrupt_init) in mobiveil_pcie_interrupt_init()
542 return rp->ops->interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
544 return mobiveil_pcie_integrated_interrupt_init(pcie); in mobiveil_pcie_interrupt_init()
547 static bool mobiveil_pcie_is_bridge(struct mobiveil_pcie *pcie) in mobiveil_pcie_is_bridge() argument
551 header_type = mobiveil_csr_readb(pcie, PCI_HEADER_TYPE); in mobiveil_pcie_is_bridge()
557 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie) in mobiveil_pcie_host_probe() argument
559 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_host_probe()
560 struct pci_host_bridge *bridge = rp->bridge; in mobiveil_pcie_host_probe()
561 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_host_probe()
564 ret = mobiveil_pcie_parse_dt(pcie); in mobiveil_pcie_host_probe()
570 if (!mobiveil_pcie_is_bridge(pcie)) in mobiveil_pcie_host_probe()
571 return -ENODEV; in mobiveil_pcie_host_probe()
577 ret = mobiveil_host_init(pcie, false); in mobiveil_pcie_host_probe()
583 ret = mobiveil_pcie_interrupt_init(pcie); in mobiveil_pcie_host_probe()
590 bridge->sysdata = pcie; in mobiveil_pcie_host_probe()
591 bridge->ops = &mobiveil_pcie_ops; in mobiveil_pcie_host_probe()
593 ret = mobiveil_bringup_link(pcie); in mobiveil_pcie_host_probe()
595 dev_info(dev, "link bring-up failed\n"); in mobiveil_pcie_host_probe()