Lines Matching full:aardvark

3  * Driver for the Aardvark PCIe controller, used on Marvell Armada
67 /* Aardvark Control registers */
526 	 * Note that this Aardvark PCI Bridge does not have compliant Type 1  in advk_pcie_setup_hw()
527 	 * Configuration Space and it even cannot be accessed via Aardvark's  in advk_pcie_setup_hw()
529 	 * available in internal Aardvark registers starting at offset 0x0  in advk_pcie_setup_hw()
534 	 * access to configuration space via internal Aardvark registers or  in advk_pcie_setup_hw()
725 		 * So return -EAGAIN and caller (pci-aardvark.c driver) will  in advk_pcie_check_pio_status()
865 		 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0.  in advk_pci_bridge_emul_pcie_conf_read()
966 	/* Aardvark HW provides PCIe Capability structure in version 2 */  in advk_sw_pci_bridge_init()
1539 		 * Aardvark hardware allows to configure also PCIe window  in advk_pcie_probe()
1719 MODULE_DESCRIPTION("Aardvark PCIe controller");