Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
28 #include "../pci-bridge-emul.h"
30 /* PCIe core registers */
31 #define PCIE_CORE_DEV_ID_REG 0x0
32 #define PCIE_CORE_CMD_STATUS_REG 0x4
33 #define PCIE_CORE_DEV_REV_REG 0x8
34 #define PCIE_CORE_PCIEXP_CAP 0xc0
35 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
45 #define PIO_BASE_ADDR 0x4000
46 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
47 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
49 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
52 #define PIO_COMPLETION_STATUS_OK 0
58 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
59 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
60 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
61 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
62 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
63 #define PIO_START (PIO_BASE_ADDR + 0x1c)
64 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
65 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
68 #define CONTROL_BASE_ADDR 0x4800
69 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
70 #define PCIE_GEN_SEL_MSK 0x3
71 #define PCIE_GEN_SEL_SHIFT 0x0
72 #define SPEED_GEN_1 0
77 #define LANE_CNT_MSK 0x18
78 #define LANE_CNT_SHIFT 0x3
79 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
88 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
89 #define HOT_RESET_GEN BIT(0)
90 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
91 #define PCIE_CORE_CTRL2_RESERVED 0x7
96 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
99 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
100 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
102 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
106 #define PCIE_ISR0_ALL_MASK GENMASK(31, 0)
107 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
108 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
112 #define PCIE_ISR1_ALL_MASK GENMASK(31, 0)
113 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
114 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
115 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
116 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
117 #define PCIE_MSI_ALL_MASK GENMASK(31, 0)
118 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
119 #define PCIE_MSI_DATA_MASK GENMASK(15, 0)
121 /* PCIe window configuration */
122 #define OB_WIN_BASE_ADDR 0x4c00
123 #define OB_WIN_BLOCK_SIZE 0x20
128 #define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
129 #define OB_WIN_ENABLE BIT(0)
130 #define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
131 #define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
132 #define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
133 #define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
134 #define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
135 #define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
136 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
153 #define OB_WIN_TYPE_MASK GENMASK(3, 0)
154 #define OB_WIN_TYPE_SHIFT 0
155 #define OB_WIN_TYPE_MEM 0x0
156 #define OB_WIN_TYPE_IO 0x4
157 #define OB_WIN_TYPE_CONFIG_TYPE0 0x8
158 #define OB_WIN_TYPE_CONFIG_TYPE1 0x9
159 #define OB_WIN_TYPE_MSG 0xc
162 #define LMI_BASE_ADDR 0x6000
163 #define CFG_REG (LMI_BASE_ADDR + 0x0)
165 #define LTSSM_MASK 0x3f
166 #define RC_BAR_CONFIG 0x300
170 LTSSM_DETECT_QUIET = 0x0,
171 LTSSM_DETECT_ACTIVE = 0x1,
172 LTSSM_POLLING_ACTIVE = 0x2,
173 LTSSM_POLLING_COMPLIANCE = 0x3,
174 LTSSM_POLLING_CONFIGURATION = 0x4,
175 LTSSM_CONFIG_LINKWIDTH_START = 0x5,
176 LTSSM_CONFIG_LINKWIDTH_ACCEPT = 0x6,
177 LTSSM_CONFIG_LANENUM_ACCEPT = 0x7,
178 LTSSM_CONFIG_LANENUM_WAIT = 0x8,
179 LTSSM_CONFIG_COMPLETE = 0x9,
180 LTSSM_CONFIG_IDLE = 0xa,
181 LTSSM_RECOVERY_RCVR_LOCK = 0xb,
182 LTSSM_RECOVERY_SPEED = 0xc,
183 LTSSM_RECOVERY_RCVR_CFG = 0xd,
184 LTSSM_RECOVERY_IDLE = 0xe,
185 LTSSM_L0 = 0x10,
186 LTSSM_RX_L0S_ENTRY = 0x11,
187 LTSSM_RX_L0S_IDLE = 0x12,
188 LTSSM_RX_L0S_FTS = 0x13,
189 LTSSM_TX_L0S_ENTRY = 0x14,
190 LTSSM_TX_L0S_IDLE = 0x15,
191 LTSSM_TX_L0S_FTS = 0x16,
192 LTSSM_L1_ENTRY = 0x17,
193 LTSSM_L1_IDLE = 0x18,
194 LTSSM_L2_IDLE = 0x19,
195 LTSSM_L2_TRANSMIT_WAKE = 0x1a,
196 LTSSM_DISABLED = 0x20,
197 LTSSM_LOOPBACK_ENTRY_MASTER = 0x21,
198 LTSSM_LOOPBACK_ACTIVE_MASTER = 0x22,
199 LTSSM_LOOPBACK_EXIT_MASTER = 0x23,
200 LTSSM_LOOPBACK_ENTRY_SLAVE = 0x24,
201 LTSSM_LOOPBACK_ACTIVE_SLAVE = 0x25,
202 LTSSM_LOOPBACK_EXIT_SLAVE = 0x26,
203 LTSSM_HOT_RESET = 0x27,
204 LTSSM_RECOVERY_EQUALIZATION_PHASE0 = 0x28,
205 LTSSM_RECOVERY_EQUALIZATION_PHASE1 = 0x29,
206 LTSSM_RECOVERY_EQUALIZATION_PHASE2 = 0x2a,
207 LTSSM_RECOVERY_EQUALIZATION_PHASE3 = 0x2b,
210 #define VENDOR_ID_REG (LMI_BASE_ADDR + 0x44)
212 /* PCIe core controller registers */
213 #define CTRL_CORE_BASE_ADDR 0x18000
214 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
215 #define CTRL_MODE_SHIFT 0x0
216 #define CTRL_MODE_MASK 0x1
217 #define PCIE_CORE_MODE_DIRECT 0x0
218 #define PCIE_CORE_MODE_COMMAND 0x1
220 /* PCIe Central Interrupts Registers */
221 #define CENTRAL_INT_BASE_ADDR 0x1b000
222 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
223 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
224 #define PCIE_IRQ_CMDQ_INT BIT(0)
242 #define PCIE_IRQ_ALL_MASK GENMASK(31, 0)
246 #define PCIE_CONFIG_RD_TYPE0 0x8
247 #define PCIE_CONFIG_RD_TYPE1 0x9
248 #define PCIE_CONFIG_WR_TYPE0 0xa
249 #define PCIE_CONFIG_WR_TYPE1 0xb
251 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
252 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
253 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
254 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
270 #define CFG_RD_CRS_VAL 0xffff0001
299 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
301 writel(val, pcie->base + reg); in advk_writel()
304 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
306 return readl(pcie->base + reg); in advk_readl()
309 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
314 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
319 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
321 /* check if LTSSM is in normal operation - some L* state */ in advk_pcie_link_up()
322 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
326 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
329 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_active()
336 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
340 static inline bool advk_pcie_link_training(struct advk_pcie *pcie) in advk_pcie_link_training() argument
343 * According to PCIe Base specification 3.0, Table 4-14: Link in advk_pcie_link_training()
347 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_training()
354 static int advk_pcie_wait_for_link(struct advk_pcie *pcie) in advk_pcie_wait_for_link() argument
359 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { in advk_pcie_wait_for_link()
360 if (advk_pcie_link_up(pcie)) in advk_pcie_wait_for_link()
361 return 0; in advk_pcie_wait_for_link()
366 return -ETIMEDOUT; in advk_pcie_wait_for_link()
369 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie) in advk_pcie_wait_for_retrain() argument
373 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) { in advk_pcie_wait_for_retrain()
374 if (advk_pcie_link_training(pcie)) in advk_pcie_wait_for_retrain()
380 static void advk_pcie_issue_perst(struct advk_pcie *pcie) in advk_pcie_issue_perst() argument
382 if (!pcie->reset_gpio) in advk_pcie_issue_perst()
386 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n"); in advk_pcie_issue_perst()
387 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in advk_pcie_issue_perst()
389 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in advk_pcie_issue_perst()
392 static void advk_pcie_train_link(struct advk_pcie *pcie) in advk_pcie_train_link() argument
394 struct device *dev = &pcie->pdev->dev; in advk_pcie_train_link()
399 * Setup PCIe rev / gen compliance based on device tree property in advk_pcie_train_link()
400 * 'max-link-speed' which also forces maximal link speed. in advk_pcie_train_link()
402 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
404 if (pcie->link_gen == 3) in advk_pcie_train_link()
406 else if (pcie->link_gen == 2) in advk_pcie_train_link()
410 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
413 * Set maximal link speed value also into PCIe Link Control 2 register. in advk_pcie_train_link()
417 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
419 if (pcie->link_gen == 3) in advk_pcie_train_link()
421 else if (pcie->link_gen == 2) in advk_pcie_train_link()
425 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL2); in advk_pcie_train_link()
427 /* Enable link training after selecting PCIe generation */ in advk_pcie_train_link()
428 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
430 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_train_link()
433 * Reset PCIe card via PERST# signal. Some cards are not detected in advk_pcie_train_link()
434 * during link training when they are in some non-initial state. in advk_pcie_train_link()
436 advk_pcie_issue_perst(pcie); in advk_pcie_train_link()
446 * So wait until PCIe link is up. Function advk_pcie_wait_for_link() in advk_pcie_train_link()
449 ret = advk_pcie_wait_for_link(pcie); in advk_pcie_train_link()
450 if (ret < 0) in advk_pcie_train_link()
457 * Set PCIe address window register which could be used for memory
460 static void advk_pcie_set_ob_win(struct advk_pcie *pcie, u8 win_num, in advk_pcie_set_ob_win() argument
464 advk_writel(pcie, OB_WIN_ENABLE | in advk_pcie_set_ob_win()
466 advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num)); in advk_pcie_set_ob_win()
467 advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num)); in advk_pcie_set_ob_win()
468 advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num)); in advk_pcie_set_ob_win()
469 advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num)); in advk_pcie_set_ob_win()
470 advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num)); in advk_pcie_set_ob_win()
471 advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num)); in advk_pcie_set_ob_win()
474 static void advk_pcie_disable_ob_win(struct advk_pcie *pcie, u8 win_num) in advk_pcie_disable_ob_win() argument
476 advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num)); in advk_pcie_disable_ob_win()
477 advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num)); in advk_pcie_disable_ob_win()
478 advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num)); in advk_pcie_disable_ob_win()
479 advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num)); in advk_pcie_disable_ob_win()
480 advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num)); in advk_pcie_disable_ob_win()
481 advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num)); in advk_pcie_disable_ob_win()
482 advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num)); in advk_pcie_disable_ob_win()
485 static void advk_pcie_setup_hw(struct advk_pcie *pcie) in advk_pcie_setup_hw() argument
491 * Configure PCIe Reference clock. Direction is from the PCIe in advk_pcie_setup_hw()
493 * Reference clock differential signal off-chip and disable in advk_pcie_setup_hw()
494 * receiving off-chip differential signal. in advk_pcie_setup_hw()
496 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
499 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG); in advk_pcie_setup_hw()
502 reg = advk_readl(pcie, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
505 advk_writel(pcie, reg, CTRL_CONFIG_REG); in advk_pcie_setup_hw()
508 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
510 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
513 * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab. in advk_pcie_setup_hw()
516 * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround in advk_pcie_setup_hw()
520 advk_writel(pcie, reg, VENDOR_ID_REG); in advk_pcie_setup_hw()
523 * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), in advk_pcie_setup_hw()
524 * because the default value is Mass storage controller (0x010400). in advk_pcie_setup_hw()
529 * available in internal Aardvark registers starting at offset 0x0 in advk_pcie_setup_hw()
530 * and is reported as Type 0. In range 0x10 - 0x34 it has totally in advk_pcie_setup_hw()
537 reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
538 reg &= ~0xffffff00; in advk_pcie_setup_hw()
540 advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); in advk_pcie_setup_hw()
543 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
545 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in advk_pcie_setup_hw()
552 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in advk_pcie_setup_hw()
554 /* Set PCIe Device Control register */ in advk_pcie_setup_hw()
555 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
562 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL); in advk_pcie_setup_hw()
564 /* Program PCIe Control 2 to disable strict ordering */ in advk_pcie_setup_hw()
567 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
570 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
573 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in advk_pcie_setup_hw()
576 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
578 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
581 advk_writel(pcie, PCIE_MSI_ALL_MASK, PCIE_MSI_STATUS_REG); in advk_pcie_setup_hw()
582 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG); in advk_pcie_setup_hw()
583 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG); in advk_pcie_setup_hw()
584 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG); in advk_pcie_setup_hw()
589 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG); in advk_pcie_setup_hw()
591 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG); in advk_pcie_setup_hw()
594 advk_writel(pcie, ~(u32)PCIE_MSI_ALL_MASK, PCIE_MSI_MASK_REG); in advk_pcie_setup_hw()
598 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG); in advk_pcie_setup_hw()
603 * configurations (Default User Field: 0xD0074CFC) in advk_pcie_setup_hw()
605 * the outbound transactions. Thus, PCIe address in advk_pcie_setup_hw()
610 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
612 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in advk_pcie_setup_hw()
616 * is not required to configure PCIe address for in advk_pcie_setup_hw()
619 advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS); in advk_pcie_setup_hw()
627 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_setup_hw()
629 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_setup_hw()
632 * Configure PCIe address windows for non-memory or in advk_pcie_setup_hw()
633 * non-transparent access as by default PCIe uses in advk_pcie_setup_hw()
636 for (i = 0; i < pcie->wins_count; i++) in advk_pcie_setup_hw()
637 advk_pcie_set_ob_win(pcie, i, in advk_pcie_setup_hw()
638 pcie->wins[i].match, pcie->wins[i].remap, in advk_pcie_setup_hw()
639 pcie->wins[i].mask, pcie->wins[i].actions); in advk_pcie_setup_hw()
641 /* Disable remaining PCIe outbound windows */ in advk_pcie_setup_hw()
642 for (i = pcie->wins_count; i < OB_WIN_COUNT; i++) in advk_pcie_setup_hw()
643 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_setup_hw()
645 advk_pcie_train_link(pcie); in advk_pcie_setup_hw()
648 static int advk_pcie_check_pio_status(struct advk_pcie *pcie, bool allow_crs, u32 *val) in advk_pcie_check_pio_status() argument
650 struct device *dev = &pcie->pdev->dev; in advk_pcie_check_pio_status()
656 reg = advk_readl(pcie, PIO_STAT); in advk_pcie_check_pio_status()
667 * a read value of 0xFFFFFFFF. in advk_pcie_check_pio_status()
670 * with a read value of 0xFFFF0001. in advk_pcie_check_pio_status()
679 ret = -EFAULT; in advk_pcie_check_pio_status()
684 *val = advk_readl(pcie, PIO_RD_DATA); in advk_pcie_check_pio_status()
687 ret = 0; in advk_pcie_check_pio_status()
691 ret = -EOPNOTSUPP; in advk_pcie_check_pio_status()
695 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
701 * read-data value of 0001h for the Vendor ID field and in advk_pcie_check_pio_status()
709 ret = 0; in advk_pcie_check_pio_status()
712 /* PCIe r4.0, sec 2.3.2, says: in advk_pcie_check_pio_status()
714 * must re-issue the Configuration Request as a new Request. in advk_pcie_check_pio_status()
717 * the Root Complex must re-issue the Configuration Request as in advk_pcie_check_pio_status()
725 * So return -EAGAIN and caller (pci-aardvark.c driver) will in advk_pcie_check_pio_status()
726 * re-issue request again up to the PIO_RETRY_CNT retries. in advk_pcie_check_pio_status()
729 ret = -EAGAIN; in advk_pcie_check_pio_status()
733 ret = -ECANCELED; in advk_pcie_check_pio_status()
737 ret = -EINVAL; in advk_pcie_check_pio_status()
745 str_posted = "Non-posted"; in advk_pcie_check_pio_status()
750 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS)); in advk_pcie_check_pio_status()
755 static int advk_pcie_wait_pio(struct advk_pcie *pcie) in advk_pcie_wait_pio() argument
757 struct device *dev = &pcie->pdev->dev; in advk_pcie_wait_pio()
763 start = advk_readl(pcie, PIO_START); in advk_pcie_wait_pio()
764 isr = advk_readl(pcie, PIO_ISR); in advk_pcie_wait_pio()
771 return -ETIMEDOUT; in advk_pcie_wait_pio()
778 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_read() local
782 *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_read()
791 __le32 *cfgspace = (__le32 *)&bridge->conf; in advk_pci_bridge_emul_base_conf_read()
793 if (advk_readl(pcie, PCIE_CORE_CTRL1_REG) & HOT_RESET_GEN) in advk_pci_bridge_emul_base_conf_read()
810 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_base_conf_write() local
814 advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); in advk_pci_bridge_emul_base_conf_write()
819 u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
824 advk_writel(pcie, val, PCIE_CORE_CTRL1_REG); in advk_pci_bridge_emul_base_conf_write()
837 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_read() local
846 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_read()
847 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE; in advk_pci_bridge_emul_pcie_conf_read()
848 *value |= le16_to_cpu(bridge->pcie_conf.rootctl) & PCI_EXP_RTCTL_CRSSVE; in advk_pci_bridge_emul_pcie_conf_read()
854 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_read()
855 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG); in advk_pci_bridge_emul_pcie_conf_read()
863 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
865 * PCI_EXP_LNKCAP_DLLLARC bit is hardwired in aardvark HW to 0. in advk_pci_bridge_emul_pcie_conf_read()
876 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) & in advk_pci_bridge_emul_pcie_conf_read()
878 if (advk_pcie_link_training(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
880 if (advk_pcie_link_active(pcie)) in advk_pci_bridge_emul_pcie_conf_read()
888 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_read()
900 struct advk_pcie *pcie = bridge->data; in advk_pci_bridge_emul_pcie_conf_write() local
904 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
908 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg); in advk_pci_bridge_emul_pcie_conf_write()
910 advk_pcie_wait_for_retrain(pcie); in advk_pci_bridge_emul_pcie_conf_write()
915 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) & in advk_pci_bridge_emul_pcie_conf_write()
917 if ((new & PCI_EXP_RTCTL_PMEIE) == 0) in advk_pci_bridge_emul_pcie_conf_write()
919 advk_writel(pcie, val, PCIE_ISR0_MASK_REG); in advk_pci_bridge_emul_pcie_conf_write()
925 advk_writel(pcie, new, PCIE_ISR0_REG); in advk_pci_bridge_emul_pcie_conf_write()
941 * Initialize the configuration space of the PCI-to-PCI bridge
942 * associated with the given PCIe interface.
944 static int advk_sw_pci_bridge_init(struct advk_pcie *pcie) in advk_sw_pci_bridge_init() argument
946 struct pci_bridge_emul *bridge = &pcie->bridge; in advk_sw_pci_bridge_init()
948 bridge->conf.vendor = in advk_sw_pci_bridge_init()
949 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff); in advk_sw_pci_bridge_init()
950 bridge->conf.device = in advk_sw_pci_bridge_init()
951 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16); in advk_sw_pci_bridge_init()
952 bridge->conf.class_revision = in advk_sw_pci_bridge_init()
953 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff); in advk_sw_pci_bridge_init()
956 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
957 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in advk_sw_pci_bridge_init()
960 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
961 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64); in advk_sw_pci_bridge_init()
964 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE; in advk_sw_pci_bridge_init()
966 /* Aardvark HW provides PCIe Capability structure in version 2 */ in advk_sw_pci_bridge_init()
967 bridge->pcie_conf.cap = cpu_to_le16(2); in advk_sw_pci_bridge_init()
970 bridge->pcie_conf.rootcap = cpu_to_le16(PCI_EXP_RTCAP_CRSVIS); in advk_sw_pci_bridge_init()
972 bridge->has_pcie = true; in advk_sw_pci_bridge_init()
973 bridge->data = pcie; in advk_sw_pci_bridge_init()
974 bridge->ops = &advk_pci_bridge_emul_ops; in advk_sw_pci_bridge_init()
976 return pci_bridge_emul_init(bridge, 0); in advk_sw_pci_bridge_init()
979 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus, in advk_pcie_valid_device() argument
982 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0) in advk_pcie_valid_device()
986 * If the link goes down after we check for link-up, nothing bad in advk_pcie_valid_device()
989 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie)) in advk_pcie_valid_device()
995 static bool advk_pcie_pio_is_running(struct advk_pcie *pcie) in advk_pcie_pio_is_running() argument
997 struct device *dev = &pcie->pdev->dev; in advk_pcie_pio_is_running()
1003 * SError Interrupt on CPU0, code 0xbf000002 -- SError in advk_pcie_pio_is_running()
1004 * Kernel panic - not syncing: Asynchronous SError Interrupt in advk_pcie_pio_is_running()
1013 * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit: in advk_pcie_pio_is_running()
1014 * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 in advk_pcie_pio_is_running()
1016 if (advk_readl(pcie, PIO_START)) { in advk_pcie_pio_is_running()
1027 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_rd_conf() local
1033 if (!advk_pcie_valid_device(pcie, bus, devfn)) { in advk_pcie_rd_conf()
1034 *val = 0xffffffff; in advk_pcie_rd_conf()
1039 return pci_bridge_emul_conf_read(&pcie->bridge, where, in advk_pcie_rd_conf()
1048 (le16_to_cpu(pcie->bridge.pcie_conf.rootctl) & in advk_pcie_rd_conf()
1051 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_rd_conf()
1055 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_rd_conf()
1057 if (pci_is_root_bus(bus->parent)) in advk_pcie_rd_conf()
1061 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_rd_conf()
1064 reg = PCIE_CONF_ADDR(bus->number, devfn, where); in advk_pcie_rd_conf()
1065 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_rd_conf()
1066 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_rd_conf()
1069 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB); in advk_pcie_rd_conf()
1071 retry_count = 0; in advk_pcie_rd_conf()
1074 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_rd_conf()
1075 advk_writel(pcie, 1, PIO_START); in advk_pcie_rd_conf()
1077 ret = advk_pcie_wait_pio(pcie); in advk_pcie_rd_conf()
1078 if (ret < 0) in advk_pcie_rd_conf()
1084 ret = advk_pcie_check_pio_status(pcie, allow_crs, val); in advk_pcie_rd_conf()
1085 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_rd_conf()
1087 if (ret < 0) in advk_pcie_rd_conf()
1091 *val = (*val >> (8 * (where & 3))) & 0xff; in advk_pcie_rd_conf()
1093 *val = (*val >> (8 * (where & 3))) & 0xffff; in advk_pcie_rd_conf()
1108 *val = 0xffffffff; in advk_pcie_rd_conf()
1115 struct advk_pcie *pcie = bus->sysdata; in advk_pcie_wr_conf() local
1117 u32 data_strobe = 0x0; in advk_pcie_wr_conf()
1122 if (!advk_pcie_valid_device(pcie, bus, devfn)) in advk_pcie_wr_conf()
1126 return pci_bridge_emul_conf_write(&pcie->bridge, where, in advk_pcie_wr_conf()
1132 if (advk_pcie_pio_is_running(pcie)) in advk_pcie_wr_conf()
1136 reg = advk_readl(pcie, PIO_CTRL); in advk_pcie_wr_conf()
1138 if (pci_is_root_bus(bus->parent)) in advk_pcie_wr_conf()
1142 advk_writel(pcie, reg, PIO_CTRL); in advk_pcie_wr_conf()
1145 reg = PCIE_CONF_ADDR(bus->number, devfn, where); in advk_pcie_wr_conf()
1146 advk_writel(pcie, reg, PIO_ADDR_LS); in advk_pcie_wr_conf()
1147 advk_writel(pcie, 0, PIO_ADDR_MS); in advk_pcie_wr_conf()
1150 offset = where & 0x3; in advk_pcie_wr_conf()
1152 data_strobe = GENMASK(size - 1, 0) << offset; in advk_pcie_wr_conf()
1155 advk_writel(pcie, reg, PIO_WR_DATA); in advk_pcie_wr_conf()
1158 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB); in advk_pcie_wr_conf()
1160 retry_count = 0; in advk_pcie_wr_conf()
1163 advk_writel(pcie, 1, PIO_ISR); in advk_pcie_wr_conf()
1164 advk_writel(pcie, 1, PIO_START); in advk_pcie_wr_conf()
1166 ret = advk_pcie_wait_pio(pcie); in advk_pcie_wr_conf()
1167 if (ret < 0) in advk_pcie_wr_conf()
1172 ret = advk_pcie_check_pio_status(pcie, false, NULL); in advk_pcie_wr_conf()
1173 } while (ret == -EAGAIN && retry_count < PIO_RETRY_CNT); in advk_pcie_wr_conf()
1175 return ret < 0 ? PCIBIOS_SET_FAILED : PCIBIOS_SUCCESSFUL; in advk_pcie_wr_conf()
1186 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data); in advk_msi_irq_compose_msi_msg() local
1187 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg); in advk_msi_irq_compose_msi_msg()
1189 msg->address_lo = lower_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1190 msg->address_hi = upper_32_bits(msi_msg); in advk_msi_irq_compose_msi_msg()
1191 msg->data = data->hwirq; in advk_msi_irq_compose_msi_msg()
1197 return -EINVAL; in advk_msi_set_affinity()
1204 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_alloc() local
1207 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1208 hwirq = bitmap_find_free_region(pcie->msi_used, MSI_IRQ_NUM, in advk_msi_irq_domain_alloc()
1210 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_alloc()
1211 if (hwirq < 0) in advk_msi_irq_domain_alloc()
1212 return -ENOSPC; in advk_msi_irq_domain_alloc()
1214 for (i = 0; i < nr_irqs; i++) in advk_msi_irq_domain_alloc()
1216 &pcie->msi_bottom_irq_chip, in advk_msi_irq_domain_alloc()
1217 domain->host_data, handle_simple_irq, in advk_msi_irq_domain_alloc()
1220 return 0; in advk_msi_irq_domain_alloc()
1227 struct advk_pcie *pcie = domain->host_data; in advk_msi_irq_domain_free() local
1229 mutex_lock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1230 bitmap_release_region(pcie->msi_used, d->hwirq, order_base_2(nr_irqs)); in advk_msi_irq_domain_free()
1231 mutex_unlock(&pcie->msi_used_lock); in advk_msi_irq_domain_free()
1241 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_mask() local
1246 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1247 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1249 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_mask()
1250 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_mask()
1255 struct advk_pcie *pcie = d->domain->host_data; in advk_pcie_irq_unmask() local
1260 raw_spin_lock_irqsave(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1261 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1263 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG); in advk_pcie_irq_unmask()
1264 raw_spin_unlock_irqrestore(&pcie->irq_lock, flags); in advk_pcie_irq_unmask()
1270 struct advk_pcie *pcie = h->host_data; in advk_pcie_irq_map() local
1274 irq_set_chip_and_handler(virq, &pcie->irq_chip, in advk_pcie_irq_map()
1276 irq_set_chip_data(virq, pcie); in advk_pcie_irq_map()
1278 return 0; in advk_pcie_irq_map()
1286 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_msi_irq_domain() argument
1288 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_msi_irq_domain()
1289 struct device_node *node = dev->of_node; in advk_pcie_init_msi_irq_domain()
1294 mutex_init(&pcie->msi_used_lock); in advk_pcie_init_msi_irq_domain()
1296 bottom_ic = &pcie->msi_bottom_irq_chip; in advk_pcie_init_msi_irq_domain()
1298 bottom_ic->name = "MSI"; in advk_pcie_init_msi_irq_domain()
1299 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg; in advk_pcie_init_msi_irq_domain()
1300 bottom_ic->irq_set_affinity = advk_msi_set_affinity; in advk_pcie_init_msi_irq_domain()
1302 msi_ic = &pcie->msi_irq_chip; in advk_pcie_init_msi_irq_domain()
1303 msi_ic->name = "advk-MSI"; in advk_pcie_init_msi_irq_domain()
1305 msi_di = &pcie->msi_domain_info; in advk_pcie_init_msi_irq_domain()
1306 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | in advk_pcie_init_msi_irq_domain()
1308 msi_di->chip = msi_ic; in advk_pcie_init_msi_irq_domain()
1310 msi_msg_phys = virt_to_phys(&pcie->msi_msg); in advk_pcie_init_msi_irq_domain()
1312 advk_writel(pcie, lower_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1314 advk_writel(pcie, upper_32_bits(msi_msg_phys), in advk_pcie_init_msi_irq_domain()
1317 pcie->msi_inner_domain = in advk_pcie_init_msi_irq_domain()
1319 &advk_msi_domain_ops, pcie); in advk_pcie_init_msi_irq_domain()
1320 if (!pcie->msi_inner_domain) in advk_pcie_init_msi_irq_domain()
1321 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1323 pcie->msi_domain = in advk_pcie_init_msi_irq_domain()
1325 msi_di, pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1326 if (!pcie->msi_domain) { in advk_pcie_init_msi_irq_domain()
1327 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_init_msi_irq_domain()
1328 return -ENOMEM; in advk_pcie_init_msi_irq_domain()
1331 return 0; in advk_pcie_init_msi_irq_domain()
1334 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_msi_irq_domain() argument
1336 irq_domain_remove(pcie->msi_domain); in advk_pcie_remove_msi_irq_domain()
1337 irq_domain_remove(pcie->msi_inner_domain); in advk_pcie_remove_msi_irq_domain()
1340 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie) in advk_pcie_init_irq_domain() argument
1342 struct device *dev = &pcie->pdev->dev; in advk_pcie_init_irq_domain()
1343 struct device_node *node = dev->of_node; in advk_pcie_init_irq_domain()
1346 int ret = 0; in advk_pcie_init_irq_domain()
1348 raw_spin_lock_init(&pcie->irq_lock); in advk_pcie_init_irq_domain()
1352 dev_err(dev, "No PCIe Intc node found\n"); in advk_pcie_init_irq_domain()
1353 return -ENODEV; in advk_pcie_init_irq_domain()
1356 irq_chip = &pcie->irq_chip; in advk_pcie_init_irq_domain()
1358 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq", in advk_pcie_init_irq_domain()
1360 if (!irq_chip->name) { in advk_pcie_init_irq_domain()
1361 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1365 irq_chip->irq_mask = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1366 irq_chip->irq_mask_ack = advk_pcie_irq_mask; in advk_pcie_init_irq_domain()
1367 irq_chip->irq_unmask = advk_pcie_irq_unmask; in advk_pcie_init_irq_domain()
1369 pcie->irq_domain = in advk_pcie_init_irq_domain()
1371 &advk_pcie_irq_domain_ops, pcie); in advk_pcie_init_irq_domain()
1372 if (!pcie->irq_domain) { in advk_pcie_init_irq_domain()
1374 ret = -ENOMEM; in advk_pcie_init_irq_domain()
1383 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie) in advk_pcie_remove_irq_domain() argument
1385 irq_domain_remove(pcie->irq_domain); in advk_pcie_remove_irq_domain()
1388 static void advk_pcie_handle_msi(struct advk_pcie *pcie) in advk_pcie_handle_msi() argument
1393 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG); in advk_pcie_handle_msi()
1394 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1397 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) { in advk_pcie_handle_msi()
1401 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG); in advk_pcie_handle_msi()
1402 virq = irq_find_mapping(pcie->msi_inner_domain, msi_idx); in advk_pcie_handle_msi()
1406 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING, in advk_pcie_handle_msi()
1410 static void advk_pcie_handle_int(struct advk_pcie *pcie) in advk_pcie_handle_int() argument
1416 isr0_val = advk_readl(pcie, PCIE_ISR0_REG); in advk_pcie_handle_int()
1417 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG); in advk_pcie_handle_int()
1420 isr1_val = advk_readl(pcie, PCIE_ISR1_REG); in advk_pcie_handle_int()
1421 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG); in advk_pcie_handle_int()
1426 advk_pcie_handle_msi(pcie); in advk_pcie_handle_int()
1429 for (i = 0; i < PCI_NUM_INTX; i++) { in advk_pcie_handle_int()
1433 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i), in advk_pcie_handle_int()
1436 virq = irq_find_mapping(pcie->irq_domain, i); in advk_pcie_handle_int()
1443 struct advk_pcie *pcie = arg; in advk_pcie_irq_handler() local
1446 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1450 advk_pcie_handle_int(pcie); in advk_pcie_irq_handler()
1453 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG); in advk_pcie_irq_handler()
1458 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie) in advk_pcie_disable_phy() argument
1460 phy_power_off(pcie->phy); in advk_pcie_disable_phy()
1461 phy_exit(pcie->phy); in advk_pcie_disable_phy()
1464 static int advk_pcie_enable_phy(struct advk_pcie *pcie) in advk_pcie_enable_phy() argument
1468 if (!pcie->phy) in advk_pcie_enable_phy()
1469 return 0; in advk_pcie_enable_phy()
1471 ret = phy_init(pcie->phy); in advk_pcie_enable_phy()
1475 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE); in advk_pcie_enable_phy()
1477 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1481 ret = phy_power_on(pcie->phy); in advk_pcie_enable_phy()
1482 if (ret == -EOPNOTSUPP) { in advk_pcie_enable_phy()
1483 dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n"); in advk_pcie_enable_phy()
1485 phy_exit(pcie->phy); in advk_pcie_enable_phy()
1489 return 0; in advk_pcie_enable_phy()
1492 static int advk_pcie_setup_phy(struct advk_pcie *pcie) in advk_pcie_setup_phy() argument
1494 struct device *dev = &pcie->pdev->dev; in advk_pcie_setup_phy()
1495 struct device_node *node = dev->of_node; in advk_pcie_setup_phy()
1496 int ret = 0; in advk_pcie_setup_phy()
1498 pcie->phy = devm_of_phy_get(dev, node, NULL); in advk_pcie_setup_phy()
1499 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER)) in advk_pcie_setup_phy()
1500 return PTR_ERR(pcie->phy); in advk_pcie_setup_phy()
1503 if (IS_ERR(pcie->phy)) { in advk_pcie_setup_phy()
1504 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy)); in advk_pcie_setup_phy()
1505 pcie->phy = NULL; in advk_pcie_setup_phy()
1506 return 0; in advk_pcie_setup_phy()
1509 ret = advk_pcie_enable_phy(pcie); in advk_pcie_setup_phy()
1518 struct device *dev = &pdev->dev; in advk_pcie_probe()
1519 struct advk_pcie *pcie; in advk_pcie_probe() local
1526 return -ENOMEM; in advk_pcie_probe()
1528 pcie = pci_host_bridge_priv(bridge); in advk_pcie_probe()
1529 pcie->pdev = pdev; in advk_pcie_probe()
1530 platform_set_drvdata(pdev, pcie); in advk_pcie_probe()
1532 resource_list_for_each_entry(entry, &bridge->windows) { in advk_pcie_probe()
1533 resource_size_t start = entry->res->start; in advk_pcie_probe()
1534 resource_size_t size = resource_size(entry->res); in advk_pcie_probe()
1535 unsigned long type = resource_type(entry->res); in advk_pcie_probe()
1539 * Aardvark hardware allows to configure also PCIe window in advk_pcie_probe()
1540 * for config type 0 and type 1 mapping, but driver uses in advk_pcie_probe()
1542 * not use PCIe window configuration. in advk_pcie_probe()
1554 entry->offset == 0) in advk_pcie_probe()
1558 * The n-th PCIe window is configured by tuple (match, remap, mask) in advk_pcie_probe()
1561 * So every PCIe window size must be a power of two and every start in advk_pcie_probe()
1566 while (pcie->wins_count < OB_WIN_COUNT && size > 0) { in advk_pcie_probe()
1568 win_size = (1ULL << (fls64(size)-1)) | in advk_pcie_probe()
1569 (start ? (1ULL << __ffs64(start)) : 0); in advk_pcie_probe()
1571 if (win_size < 0x10000) in advk_pcie_probe()
1575 "Configuring PCIe window %d: [0x%llx-0x%llx] as %lu\n", in advk_pcie_probe()
1576 pcie->wins_count, (unsigned long long)start, in advk_pcie_probe()
1580 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_IO; in advk_pcie_probe()
1581 pcie->wins[pcie->wins_count].match = pci_pio_to_address(start); in advk_pcie_probe()
1583 pcie->wins[pcie->wins_count].actions = OB_WIN_TYPE_MEM; in advk_pcie_probe()
1584 pcie->wins[pcie->wins_count].match = start; in advk_pcie_probe()
1586 pcie->wins[pcie->wins_count].remap = start - entry->offset; in advk_pcie_probe()
1587 pcie->wins[pcie->wins_count].mask = ~(win_size - 1); in advk_pcie_probe()
1589 if (pcie->wins[pcie->wins_count].remap & (win_size - 1)) in advk_pcie_probe()
1593 size -= win_size; in advk_pcie_probe()
1594 pcie->wins_count++; in advk_pcie_probe()
1597 if (size > 0) { in advk_pcie_probe()
1598 dev_err(&pcie->pdev->dev, in advk_pcie_probe()
1599 "Invalid PCIe region [0x%llx-0x%llx]\n", in advk_pcie_probe()
1600 (unsigned long long)entry->res->start, in advk_pcie_probe()
1601 (unsigned long long)entry->res->end + 1); in advk_pcie_probe()
1602 return -EINVAL; in advk_pcie_probe()
1606 pcie->base = devm_platform_ioremap_resource(pdev, 0); in advk_pcie_probe()
1607 if (IS_ERR(pcie->base)) in advk_pcie_probe()
1608 return PTR_ERR(pcie->base); in advk_pcie_probe()
1610 irq = platform_get_irq(pdev, 0); in advk_pcie_probe()
1611 if (irq < 0) in advk_pcie_probe()
1615 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie", in advk_pcie_probe()
1616 pcie); in advk_pcie_probe()
1622 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node, in advk_pcie_probe()
1623 "reset-gpios", 0, in advk_pcie_probe()
1625 "pcie1-reset"); in advk_pcie_probe()
1626 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio); in advk_pcie_probe()
1628 if (ret == -ENOENT) { in advk_pcie_probe()
1629 pcie->reset_gpio = NULL; in advk_pcie_probe()
1631 if (ret != -EPROBE_DEFER) in advk_pcie_probe()
1632 dev_err(dev, "Failed to get reset-gpio: %i\n", in advk_pcie_probe()
1638 ret = of_pci_get_max_link_speed(dev->of_node); in advk_pcie_probe()
1639 if (ret <= 0 || ret > 3) in advk_pcie_probe()
1640 pcie->link_gen = 3; in advk_pcie_probe()
1642 pcie->link_gen = ret; in advk_pcie_probe()
1644 ret = advk_pcie_setup_phy(pcie); in advk_pcie_probe()
1648 advk_pcie_setup_hw(pcie); in advk_pcie_probe()
1650 ret = advk_sw_pci_bridge_init(pcie); in advk_pcie_probe()
1656 ret = advk_pcie_init_irq_domain(pcie); in advk_pcie_probe()
1662 ret = advk_pcie_init_msi_irq_domain(pcie); in advk_pcie_probe()
1665 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1669 bridge->sysdata = pcie; in advk_pcie_probe()
1670 bridge->ops = &advk_pcie_ops; in advk_pcie_probe()
1673 if (ret < 0) { in advk_pcie_probe()
1674 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_probe()
1675 advk_pcie_remove_irq_domain(pcie); in advk_pcie_probe()
1679 return 0; in advk_pcie_probe()
1684 struct advk_pcie *pcie = platform_get_drvdata(pdev); in advk_pcie_remove() local
1685 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in advk_pcie_remove()
1689 pci_stop_root_bus(bridge->bus); in advk_pcie_remove()
1690 pci_remove_root_bus(bridge->bus); in advk_pcie_remove()
1693 advk_pcie_remove_msi_irq_domain(pcie); in advk_pcie_remove()
1694 advk_pcie_remove_irq_domain(pcie); in advk_pcie_remove()
1697 for (i = 0; i < OB_WIN_COUNT; i++) in advk_pcie_remove()
1698 advk_pcie_disable_ob_win(pcie, i); in advk_pcie_remove()
1700 return 0; in advk_pcie_remove()
1704 { .compatible = "marvell,armada-3700-pcie", },
1711 .name = "advk-pcie",
1719 MODULE_DESCRIPTION("Aardvark PCIe controller");