Lines Matching +full:conf +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <linux/clk.h>
24 #include "../pci-bridge-emul.h"
36 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
96 struct clk *clk; member
110 writel(val, port->base + reg); in mvebu_writel()
115 return readl(port->base + reg); in mvebu_readl()
120 return port->io_target != -1 && port->io_attr != -1; in mvebu_has_ioport()
150 * BAR[0] -> internal registers (needed for MSI)
151 * BAR[1] -> covers all DRAM banks
152 * BAR[2] -> Disabled
153 * WIN[0-3] -> DRAM bank[0-3]
182 for (i = 0; i < dram->num_cs; i++) { in mvebu_pcie_setup_wins()
183 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_pcie_setup_wins()
185 mvebu_writel(port, cs->base & 0xffff0000, in mvebu_pcie_setup_wins()
189 ((cs->size - 1) & 0xffff0000) | in mvebu_pcie_setup_wins()
190 (cs->mbus_attr << 8) | in mvebu_pcie_setup_wins()
191 (dram->mbus_dram_target_id << 4) | 1, in mvebu_pcie_setup_wins()
194 size += cs->size; in mvebu_pcie_setup_wins()
198 if ((size & (size - 1)) != 0) in mvebu_pcie_setup_wins()
202 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
204 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1, in mvebu_pcie_setup_wins()
210 mvebu_writel(port, round_down(port->regs.start, SZ_1M), PCIE_BAR_LO_OFF(0)); in mvebu_pcie_setup_wins()
228 /* Enable interrupt lines A-D. */ in mvebu_pcie_setup_hw()
238 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; in mvebu_pcie_hw_rd_conf()
240 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_hw_rd_conf()
262 void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF; in mvebu_pcie_hw_wr_conf()
264 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where), in mvebu_pcie_hw_wr_conf()
292 size_t sz = 1 << (fls(size) - 1); in mvebu_pcie_del_windows()
296 size -= sz; in mvebu_pcie_del_windows()
314 size_t sz = 1 << (fls(size) - 1); in mvebu_pcie_add_windows()
320 phys_addr_t end = base + sz - 1; in mvebu_pcie_add_windows()
322 dev_err(&port->pcie->pdev->dev, in mvebu_pcie_add_windows()
323 "Could not create MBus window at [mem %pa-%pa]: %d\n", in mvebu_pcie_add_windows()
325 mvebu_pcie_del_windows(port, base - size_mapped, in mvebu_pcie_add_windows()
330 size -= sz; in mvebu_pcie_add_windows()
343 if (desired->base == cur->base && desired->remap == cur->remap && in mvebu_pcie_set_window()
344 desired->size == cur->size) in mvebu_pcie_set_window()
347 if (cur->size != 0) { in mvebu_pcie_set_window()
348 mvebu_pcie_del_windows(port, cur->base, cur->size); in mvebu_pcie_set_window()
349 cur->size = 0; in mvebu_pcie_set_window()
350 cur->base = 0; in mvebu_pcie_set_window()
359 if (desired->size == 0) in mvebu_pcie_set_window()
362 mvebu_pcie_add_windows(port, target, attribute, desired->base, in mvebu_pcie_set_window()
363 desired->size, desired->remap); in mvebu_pcie_set_window()
370 struct pci_bridge_emul_conf *conf = &port->bridge.conf; in mvebu_pcie_handle_iobase_change() local
373 if (conf->iolimit < conf->iobase || in mvebu_pcie_handle_iobase_change()
374 conf->iolimitupper < conf->iobaseupper || in mvebu_pcie_handle_iobase_change()
375 !(conf->command & PCI_COMMAND_IO)) { in mvebu_pcie_handle_iobase_change()
376 mvebu_pcie_set_window(port, port->io_target, port->io_attr, in mvebu_pcie_handle_iobase_change()
377 &desired, &port->iowin); in mvebu_pcie_handle_iobase_change()
382 dev_WARN(&port->pcie->pdev->dev, in mvebu_pcie_handle_iobase_change()
388 * We read the PCI-to-PCI bridge emulated registers, and in mvebu_pcie_handle_iobase_change()
390 * window to setup, according to the PCI-to-PCI bridge in mvebu_pcie_handle_iobase_change()
391 * specifications. iobase is the bus address, port->iowin_base in mvebu_pcie_handle_iobase_change()
394 desired.remap = ((conf->iobase & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
395 (conf->iobaseupper << 16); in mvebu_pcie_handle_iobase_change()
396 desired.base = port->pcie->io.start + desired.remap; in mvebu_pcie_handle_iobase_change()
397 desired.size = ((0xFFF | ((conf->iolimit & 0xF0) << 8) | in mvebu_pcie_handle_iobase_change()
398 (conf->iolimitupper << 16)) - in mvebu_pcie_handle_iobase_change()
402 mvebu_pcie_set_window(port, port->io_target, port->io_attr, &desired, in mvebu_pcie_handle_iobase_change()
403 &port->iowin); in mvebu_pcie_handle_iobase_change()
409 struct pci_bridge_emul_conf *conf = &port->bridge.conf; in mvebu_pcie_handle_membase_change() local
412 if (conf->memlimit < conf->membase || in mvebu_pcie_handle_membase_change()
413 !(conf->command & PCI_COMMAND_MEMORY)) { in mvebu_pcie_handle_membase_change()
414 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, in mvebu_pcie_handle_membase_change()
415 &desired, &port->memwin); in mvebu_pcie_handle_membase_change()
420 * We read the PCI-to-PCI bridge emulated registers, and in mvebu_pcie_handle_membase_change()
422 * window to setup, according to the PCI-to-PCI bridge in mvebu_pcie_handle_membase_change()
425 desired.base = ((conf->membase & 0xFFF0) << 16); in mvebu_pcie_handle_membase_change()
426 desired.size = (((conf->memlimit & 0xFFF0) << 16) | 0xFFFFF) - in mvebu_pcie_handle_membase_change()
429 mvebu_pcie_set_window(port, port->mem_target, port->mem_attr, &desired, in mvebu_pcie_handle_membase_change()
430 &port->memwin); in mvebu_pcie_handle_membase_change()
437 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_pcie_conf_read()
453 * hard-wired to zero for downstream ports in mvebu_pci_bridge_emul_pcie_conf_read()
482 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_base_conf_write()
483 struct pci_bridge_emul_conf *conf = &bridge->conf; in mvebu_pci_bridge_emul_base_conf_write() local
489 conf->command &= ~PCI_COMMAND_IO; in mvebu_pci_bridge_emul_base_conf_write()
501 * We keep bit 1 set, it is a read-only bit that in mvebu_pci_bridge_emul_base_conf_write()
505 conf->iobase |= PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_base_conf_write()
506 conf->iolimit |= PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_base_conf_write()
519 mvebu_pcie_set_local_bus_nr(port, conf->secondary_bus); in mvebu_pci_bridge_emul_base_conf_write()
531 struct mvebu_pcie_port *port = bridge->data; in mvebu_pci_bridge_emul_pcie_conf_write()
570 * Initialize the configuration space of the PCI-to-PCI bridge
575 struct pci_bridge_emul *bridge = &port->bridge; in mvebu_pci_bridge_emul_init()
579 bridge->conf.vendor = PCI_VENDOR_ID_MARVELL; in mvebu_pci_bridge_emul_init()
580 bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16; in mvebu_pci_bridge_emul_init()
581 bridge->conf.class_revision = in mvebu_pci_bridge_emul_init()
586 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_init()
587 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32; in mvebu_pci_bridge_emul_init()
594 bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver); in mvebu_pci_bridge_emul_init()
596 bridge->has_pcie = true; in mvebu_pci_bridge_emul_init()
597 bridge->data = port; in mvebu_pci_bridge_emul_init()
598 bridge->ops = &mvebu_pci_bridge_emul_ops; in mvebu_pci_bridge_emul_init()
605 return sys->private_data; in sys_to_pcie()
614 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_find_port()
615 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_find_port()
617 if (bus->number == 0 && port->devfn == devfn) in mvebu_pcie_find_port()
619 if (bus->number != 0 && in mvebu_pcie_find_port()
620 bus->number >= port->bridge.conf.secondary_bus && in mvebu_pcie_find_port()
621 bus->number <= port->bridge.conf.subordinate_bus) in mvebu_pcie_find_port()
632 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_wr_conf()
640 /* Access the emulated PCI-to-PCI bridge */ in mvebu_pcie_wr_conf()
641 if (bus->number == 0) in mvebu_pcie_wr_conf()
642 return pci_bridge_emul_conf_write(&port->bridge, where, in mvebu_pcie_wr_conf()
659 struct mvebu_pcie *pcie = bus->sysdata; in mvebu_pcie_rd_conf()
669 /* Access the emulated PCI-to-PCI bridge */ in mvebu_pcie_rd_conf()
670 if (bus->number == 0) in mvebu_pcie_rd_conf()
671 return pci_bridge_emul_conf_read(&port->bridge, where, in mvebu_pcie_rd_conf()
697 if (dev->bus->number != 0) in mvebu_pcie_align_resource()
701 * On the PCI-to-PCI bridge side, the I/O windows must have at in mvebu_pcie_align_resource()
711 if (res->flags & IORESOURCE_IO) in mvebu_pcie_align_resource()
714 else if (res->flags & IORESOURCE_MEM) in mvebu_pcie_align_resource()
727 ret = of_address_to_resource(np, 0, &port->regs); in mvebu_pcie_map_registers()
731 return devm_ioremap_resource(&pdev->dev, &port->regs); in mvebu_pcie_map_registers()
749 *tgt = -1; in mvebu_get_tgt_attr()
750 *attr = -1; in mvebu_get_tgt_attr()
754 return -EINVAL; in mvebu_get_tgt_attr()
780 return -ENOENT; in mvebu_get_tgt_attr()
790 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_suspend()
791 struct mvebu_pcie_port *port = pcie->ports + i; in mvebu_pcie_suspend()
792 port->saved_pcie_stat = mvebu_readl(port, PCIE_STAT_OFF); in mvebu_pcie_suspend()
804 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_resume()
805 struct mvebu_pcie_port *port = pcie->ports + i; in mvebu_pcie_resume()
806 mvebu_writel(port, port->saved_pcie_stat, PCIE_STAT_OFF); in mvebu_pcie_resume()
818 clk_put(port->clk); in mvebu_pcie_port_clk_put()
824 struct device *dev = &pcie->pdev->dev; in mvebu_pcie_parse_port()
828 port->pcie = pcie; in mvebu_pcie_parse_port()
830 if (of_property_read_u32(child, "marvell,pcie-port", &port->port)) { in mvebu_pcie_parse_port()
831 dev_warn(dev, "ignoring %pOF, missing pcie-port property\n", in mvebu_pcie_parse_port()
836 if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane)) in mvebu_pcie_parse_port()
837 port->lane = 0; in mvebu_pcie_parse_port()
839 port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port, in mvebu_pcie_parse_port()
840 port->lane); in mvebu_pcie_parse_port()
841 if (!port->name) { in mvebu_pcie_parse_port()
842 ret = -ENOMEM; in mvebu_pcie_parse_port()
846 port->devfn = of_pci_get_devfn(child); in mvebu_pcie_parse_port()
847 if (port->devfn < 0) in mvebu_pcie_parse_port()
850 ret = mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_MEM, in mvebu_pcie_parse_port()
851 &port->mem_target, &port->mem_attr); in mvebu_pcie_parse_port()
854 port->name); in mvebu_pcie_parse_port()
858 if (resource_size(&pcie->io) != 0) { in mvebu_pcie_parse_port()
859 mvebu_get_tgt_attr(dev->of_node, port->devfn, IORESOURCE_IO, in mvebu_pcie_parse_port()
860 &port->io_target, &port->io_attr); in mvebu_pcie_parse_port()
862 port->io_target = -1; in mvebu_pcie_parse_port()
863 port->io_attr = -1; in mvebu_pcie_parse_port()
866 reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags); in mvebu_pcie_parse_port()
867 if (reset_gpio == -EPROBE_DEFER) { in mvebu_pcie_parse_port()
875 port->reset_name = devm_kasprintf(dev, GFP_KERNEL, "%s-reset", in mvebu_pcie_parse_port()
876 port->name); in mvebu_pcie_parse_port()
877 if (!port->reset_name) { in mvebu_pcie_parse_port()
878 ret = -ENOMEM; in mvebu_pcie_parse_port()
892 port->reset_name); in mvebu_pcie_parse_port()
894 if (ret == -EPROBE_DEFER) in mvebu_pcie_parse_port()
899 port->reset_gpio = gpio_to_desc(reset_gpio); in mvebu_pcie_parse_port()
902 port->clk = of_clk_get_by_name(child, NULL); in mvebu_pcie_parse_port()
903 if (IS_ERR(port->clk)) { in mvebu_pcie_parse_port()
904 dev_err(dev, "%s: cannot get clock\n", port->name); in mvebu_pcie_parse_port()
910 clk_put(port->clk); in mvebu_pcie_parse_port()
920 devm_kfree(dev, port->reset_name); in mvebu_pcie_parse_port()
921 port->reset_name = NULL; in mvebu_pcie_parse_port()
922 devm_kfree(dev, port->name); in mvebu_pcie_parse_port()
923 port->name = NULL; in mvebu_pcie_parse_port()
931 * prior to releasing PERST. See table 2-4 in section 2.6.2 AC Specifications
938 ret = clk_prepare_enable(port->clk); in mvebu_pcie_powerup()
942 if (port->reset_gpio) { in mvebu_pcie_powerup()
945 of_property_read_u32(port->dn, "reset-delay-us", in mvebu_pcie_powerup()
950 gpiod_set_value_cansleep(port->reset_gpio, 0); in mvebu_pcie_powerup()
963 gpiod_set_value_cansleep(port->reset_gpio, 1); in mvebu_pcie_powerdown()
965 clk_disable_unprepare(port->clk); in mvebu_pcie_powerdown()
975 struct device *dev = &pcie->pdev->dev; in mvebu_pcie_parse_request_resources()
980 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem); in mvebu_pcie_parse_request_resources()
981 if (resource_size(&pcie->mem) == 0) { in mvebu_pcie_parse_request_resources()
983 return -EINVAL; in mvebu_pcie_parse_request_resources()
986 pcie->mem.name = "PCI MEM"; in mvebu_pcie_parse_request_resources()
987 pci_add_resource(&bridge->windows, &pcie->mem); in mvebu_pcie_parse_request_resources()
988 ret = devm_request_resource(dev, &iomem_resource, &pcie->mem); in mvebu_pcie_parse_request_resources()
993 mvebu_mbus_get_pcie_io_aperture(&pcie->io); in mvebu_pcie_parse_request_resources()
995 if (resource_size(&pcie->io) != 0) { in mvebu_pcie_parse_request_resources()
996 pcie->realio.flags = pcie->io.flags; in mvebu_pcie_parse_request_resources()
997 pcie->realio.start = PCIBIOS_MIN_IO; in mvebu_pcie_parse_request_resources()
998 pcie->realio.end = min_t(resource_size_t, in mvebu_pcie_parse_request_resources()
999 IO_SPACE_LIMIT - SZ_64K, in mvebu_pcie_parse_request_resources()
1000 resource_size(&pcie->io) - 1); in mvebu_pcie_parse_request_resources()
1001 pcie->realio.name = "PCI I/O"; in mvebu_pcie_parse_request_resources()
1003 pci_add_resource(&bridge->windows, &pcie->realio); in mvebu_pcie_parse_request_resources()
1004 ret = devm_request_resource(dev, &ioport_resource, &pcie->realio); in mvebu_pcie_parse_request_resources()
1027 dev_err(bridge->dev.parent, "Scanning root bridge failed"); in mvebu_pci_host_probe()
1032 if (resource_size(&pcie->io) != 0) { in mvebu_pci_host_probe()
1035 for (i = 0; i < resource_size(&pcie->realio); i += SZ_64K) in mvebu_pci_host_probe()
1036 pci_ioremap_io(i, pcie->io.start + i); in mvebu_pci_host_probe()
1039 bus = bridge->bus; in mvebu_pci_host_probe()
1052 list_for_each_entry(child, &bus->children, node) in mvebu_pci_host_probe()
1062 struct device *dev = &pdev->dev; in mvebu_pcie_probe()
1065 struct device_node *np = dev->of_node; in mvebu_pcie_probe()
1071 return -ENOMEM; in mvebu_pcie_probe()
1074 pcie->pdev = pdev; in mvebu_pcie_probe()
1083 pcie->ports = devm_kcalloc(dev, num, sizeof(*pcie->ports), GFP_KERNEL); in mvebu_pcie_probe()
1084 if (!pcie->ports) in mvebu_pcie_probe()
1085 return -ENOMEM; in mvebu_pcie_probe()
1089 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_probe()
1099 port->dn = child; in mvebu_pcie_probe()
1102 pcie->nports = i; in mvebu_pcie_probe()
1104 for (i = 0; i < pcie->nports; i++) { in mvebu_pcie_probe()
1105 struct mvebu_pcie_port *port = &pcie->ports[i]; in mvebu_pcie_probe()
1107 child = port->dn; in mvebu_pcie_probe()
1115 port->base = mvebu_pcie_map_registers(pdev, child, port); in mvebu_pcie_probe()
1116 if (IS_ERR(port->base)) { in mvebu_pcie_probe()
1117 dev_err(dev, "%s: cannot map registers\n", port->name); in mvebu_pcie_probe()
1118 port->base = NULL; in mvebu_pcie_probe()
1128 pcie->nports = i; in mvebu_pcie_probe()
1130 bridge->sysdata = pcie; in mvebu_pcie_probe()
1131 bridge->ops = &mvebu_pcie_ops; in mvebu_pcie_probe()
1132 bridge->align_resource = mvebu_pcie_align_resource; in mvebu_pcie_probe()
1138 { .compatible = "marvell,armada-xp-pcie", },
1139 { .compatible = "marvell,armada-370-pcie", },
1140 { .compatible = "marvell,dove-pcie", },
1141 { .compatible = "marvell,kirkwood-pcie", },
1151 .name = "mvebu-pcie",