Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
34 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
35 #define BRCM_PCIE_CAP_REGS 0x00ac
37 /* Broadcom STB PCIe Register Offsets */
38 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
40 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
42 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
43 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
45 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
46 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
48 #define PCIE_RC_DL_MDIO_ADDR 0x1100
49 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
50 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
52 #define PCIE_MISC_MISC_CTRL 0x4008
53 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
54 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
55 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
57 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
58 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
59 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
62 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
66 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
70 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
71 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
73 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
74 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
75 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
77 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
78 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
80 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
81 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
83 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
84 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
85 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
87 #define PCIE_MISC_PCIE_CTRL 0x4064
88 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
89 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
91 #define PCIE_MISC_PCIE_STATUS 0x4068
92 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
93 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
94 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
95 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
97 #define PCIE_MISC_REVISION 0x406c
98 #define BRCM_PCIE_HW_REV_33 0x0303
100 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
101 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
102 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
106 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
107 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
111 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
112 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
116 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
117 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
118 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
121 #define PCIE_INTR2_CPU_BASE 0x4300
122 #define PCIE_MSI_INTR2_BASE 0x4500
124 #define MSI_INT_STATUS 0x0
125 #define MSI_INT_CLR 0x8
126 #define MSI_INT_MASK_SET 0x10
127 #define MSI_INT_MASK_CLR 0x14
129 #define PCIE_EXT_CFG_DATA 0x8000
131 #define PCIE_EXT_CFG_INDEX 0x9000
136 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
137 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
139 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
140 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
141 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
142 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
144 /* PCIe parameters */
145 #define BRCM_NUM_PCIE_OUT_WINS 0x4
148 #define BRCM_INT_PCI_MSI_SHIFT 0
151 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
152 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
155 #define MDIO_PORT0 0x0
156 #define MDIO_DATA_MASK 0x7fffffff
157 #define MDIO_PORT_MASK 0xf0000
158 #define MDIO_REGAD_MASK 0xffff
159 #define MDIO_CMD_MASK 0xfff00000
160 #define MDIO_CMD_READ 0x1
161 #define MDIO_CMD_WRITE 0x0
162 #define MDIO_DATA_DONE_MASK 0x80000000
163 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
164 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
165 #define SSC_REGS_ADDR 0x1100
166 #define SET_ADDR_OFFSET 0x1f
167 #define SSC_CNTL_OFFSET 0x2
168 #define SSC_CNTL_OVRD_EN_MASK 0x8000
169 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
170 #define SSC_STATUS_OFFSET 0x1
171 #define SSC_STATUS_SSC_MASK 0x400
172 #define SSC_STATUS_PLL_LOCK_MASK 0x800
175 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
176 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
177 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
180 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
181 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
182 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
183 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
184 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
185 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
186 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
187 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
191 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
194 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
216 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
217 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
221 [RGR1_SW_INIT_1] = 0x9210,
222 [EXT_CFG_INDEX] = 0x9000,
223 [EXT_CFG_DATA] = 0x9004,
234 [RGR1_SW_INIT_1] = 0xc010,
235 [EXT_CFG_INDEX] = 0x9000,
236 [EXT_CFG_DATA] = 0x9004,
272 /* Internal PCIe Host Controller Information.*/
288 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
289 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
294 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
302 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
305 return log2_in - 15; in brcm_pcie_encode_ibar_size()
307 return 0; in brcm_pcie_encode_ibar_size()
312 u32 pkt = 0; in brcm_pcie_mdio_form_pkt()
332 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) { in brcm_pcie_mdio_read()
338 return MDIO_RD_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_read()
354 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) { in brcm_pcie_mdio_write()
359 return MDIO_WT_DONE(data) ? 0 : -EIO; in brcm_pcie_mdio_write()
366 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
372 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
374 if (ret < 0) in brcm_pcie_set_ssc()
377 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
379 if (ret < 0) in brcm_pcie_set_ssc()
384 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
386 if (ret < 0) in brcm_pcie_set_ssc()
390 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
392 if (ret < 0) in brcm_pcie_set_ssc()
398 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
402 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
404 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
405 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
408 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP); in brcm_pcie_set_gen()
410 lnkctl2 = (lnkctl2 & ~0xf) | gen; in brcm_pcie_set_gen()
411 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
414 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
424 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
425 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
429 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
431 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
436 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
443 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
449 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
452 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
456 .name = "BRCM STB PCIe MSI",
478 dev = msi->dev; in brcm_pcie_msi_isr()
480 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
481 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
483 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
484 virq = irq_find_mapping(msi->inner_domain, bit); in brcm_pcie_msi_isr()
498 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
499 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
500 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
506 return -EINVAL; in brcm_msi_set_affinity()
512 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
514 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
529 mutex_lock(&msi->lock); in brcm_msi_alloc()
530 hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0); in brcm_msi_alloc()
531 mutex_unlock(&msi->lock); in brcm_msi_alloc()
538 mutex_lock(&msi->lock); in brcm_msi_free()
539 bitmap_release_region(&msi->used, hwirq, 0); in brcm_msi_free()
540 mutex_unlock(&msi->lock); in brcm_msi_free()
546 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
551 if (hwirq < 0) in brcm_irq_domain_alloc()
555 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
557 return 0; in brcm_irq_domain_alloc()
566 brcm_msi_free(msi, d->hwirq); in brcm_irq_domain_free()
576 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
577 struct device *dev = msi->dev; in brcm_allocate_domains()
579 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
580 if (!msi->inner_domain) { in brcm_allocate_domains()
582 return -ENOMEM; in brcm_allocate_domains()
585 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
587 msi->inner_domain); in brcm_allocate_domains()
588 if (!msi->msi_domain) { in brcm_allocate_domains()
590 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
591 return -ENOMEM; in brcm_allocate_domains()
594 return 0; in brcm_allocate_domains()
599 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
600 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
603 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
605 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
609 irq_set_chained_handler(msi->irq, NULL); in brcm_msi_remove()
610 irq_set_handler_data(msi->irq, NULL); in brcm_msi_remove()
616 u32 val = __GENMASK(31, msi->legacy_shift); in brcm_msi_set_regs()
618 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
619 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
622 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI in brcm_msi_set_regs()
625 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
626 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
627 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
628 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
630 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
631 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
634 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
638 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
640 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
641 if (irq <= 0) { in brcm_pcie_enable_msi()
643 return -ENODEV; in brcm_pcie_enable_msi()
648 return -ENOMEM; in brcm_pcie_enable_msi()
650 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
651 msi->dev = dev; in brcm_pcie_enable_msi()
652 msi->base = pcie->base; in brcm_pcie_enable_msi()
653 msi->np = pcie->np; in brcm_pcie_enable_msi()
654 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
655 msi->irq = irq; in brcm_pcie_enable_msi()
656 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
658 if (msi->legacy) { in brcm_pcie_enable_msi()
659 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE; in brcm_pcie_enable_msi()
660 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
661 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
663 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
664 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
665 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
672 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
675 pcie->msi = msi; in brcm_pcie_enable_msi()
677 return 0; in brcm_pcie_enable_msi()
681 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
683 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
689 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
691 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
701 return ((PCI_SLOT(devfn) & 0x1f) << PCIE_EXT_SLOT_SHIFT) in brcm_pcie_cfg_index()
702 | ((PCI_FUNC(devfn) & 0x07) << PCIE_EXT_FUNC_SHIFT) in brcm_pcie_cfg_index()
710 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_conf() local
711 void __iomem *base = pcie->base; in brcm_pcie_map_conf()
714 /* Accesses to the RC go right to the RC registers if slot==0 */ in brcm_pcie_map_conf()
719 idx = brcm_pcie_cfg_index(bus->number, devfn, 0); in brcm_pcie_map_conf()
720 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX); in brcm_pcie_map_conf()
730 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
735 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
737 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
740 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
745 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
747 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
750 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
754 /* Perst bit has moved and assert value is 0 */ in brcm_pcie_perst_set_7278()
755 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
757 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
760 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
764 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
766 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
769 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie, in brcm_pcie_get_rc_bar2_size_and_offset() argument
773 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_rc_bar2_size_and_offset()
775 struct device *dev = pcie->dev; in brcm_pcie_get_rc_bar2_size_and_offset()
776 u64 lowest_pcie_addr = ~(u64)0; in brcm_pcie_get_rc_bar2_size_and_offset()
777 int ret, i = 0; in brcm_pcie_get_rc_bar2_size_and_offset()
778 u64 size = 0; in brcm_pcie_get_rc_bar2_size_and_offset()
780 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_rc_bar2_size_and_offset()
781 u64 pcie_beg = entry->res->start - entry->offset; in brcm_pcie_get_rc_bar2_size_and_offset()
783 size += entry->res->end - entry->res->start + 1; in brcm_pcie_get_rc_bar2_size_and_offset()
788 if (lowest_pcie_addr == ~(u64)0) { in brcm_pcie_get_rc_bar2_size_and_offset()
789 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_rc_bar2_size_and_offset()
790 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
793 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_rc_bar2_size_and_offset()
796 if (ret <= 0) { in brcm_pcie_get_rc_bar2_size_and_offset()
798 pcie->num_memc = 1; in brcm_pcie_get_rc_bar2_size_and_offset()
799 pcie->memc_size[0] = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
801 pcie->num_memc = ret; in brcm_pcie_get_rc_bar2_size_and_offset()
805 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_rc_bar2_size_and_offset()
806 size += pcie->memc_size[i]; in brcm_pcie_get_rc_bar2_size_and_offset()
808 /* System memory starts at this address in PCIe-space */ in brcm_pcie_get_rc_bar2_size_and_offset()
811 *rc_bar2_size = 1ULL << fls64(size - 1); in brcm_pcie_get_rc_bar2_size_and_offset()
815 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_rc_bar2_size_and_offset()
817 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_rc_bar2_size_and_offset()
818 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_rc_bar2_size_and_offset()
819 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_rc_bar2_size_and_offset()
820 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_rc_bar2_size_and_offset()
823 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_rc_bar2_size_and_offset()
826 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_rc_bar2_size_and_offset()
828 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_rc_bar2_size_and_offset()
829 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_rc_bar2_size_and_offset()
836 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
837 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_rc_bar2_size_and_offset()
841 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_rc_bar2_size_and_offset()
842 * region at location 0 (since we have to allow some space for in brcm_pcie_get_rc_bar2_size_and_offset()
846 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) || in brcm_pcie_get_rc_bar2_size_and_offset()
848 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n", in brcm_pcie_get_rc_bar2_size_and_offset()
850 return -EINVAL; in brcm_pcie_get_rc_bar2_size_and_offset()
853 return 0; in brcm_pcie_get_rc_bar2_size_and_offset()
856 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
858 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
860 void __iomem *base = pcie->base; in brcm_pcie_setup()
861 struct device *dev = pcie->dev; in brcm_pcie_setup()
865 int num_out_wins = 0; in brcm_pcie_setup()
871 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
875 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
885 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it in brcm_pcie_setup()
886 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. in brcm_pcie_setup()
888 if (pcie->type == BCM2711) in brcm_pcie_setup()
889 burst = 0x0; /* 128B */ in brcm_pcie_setup()
890 else if (pcie->type == BCM7278) in brcm_pcie_setup()
891 burst = 0x3; /* 512 bytes */ in brcm_pcie_setup()
893 burst = 0x2; /* 512 bytes */ in brcm_pcie_setup()
902 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size, in brcm_pcie_setup()
915 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
916 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
918 if (memc == 0) in brcm_pcie_setup()
919 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0)); in brcm_pcie_setup()
932 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
935 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
937 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
939 /* disable the PCIe->GISB memory window (RC_BAR1) */ in brcm_pcie_setup()
944 /* disable the PCIe->SCB memory window (RC_BAR3) */ in brcm_pcie_setup()
949 if (pcie->gen) in brcm_pcie_setup()
950 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_setup()
953 pcie->perst_set(pcie, 0); in brcm_pcie_setup()
957 * Intermittently check status for link-up, up to a total of 100ms. in brcm_pcie_setup()
959 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_setup()
962 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_setup()
964 return -ENODEV; in brcm_pcie_setup()
967 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
968 dev_err(dev, "PCIe misconfigured; is in EP mode\n"); in brcm_pcie_setup()
969 return -EINVAL; in brcm_pcie_setup()
972 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
973 res = entry->res; in brcm_pcie_setup()
979 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
980 return -EINVAL; in brcm_pcie_setup()
983 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
984 res->start - entry->offset, in brcm_pcie_setup()
989 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
991 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1000 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1003 u32p_replace_bits(&tmp, 0x060400, in brcm_pcie_setup()
1007 if (pcie->ssc) { in brcm_pcie_setup()
1008 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_setup()
1009 if (ret == 0) in brcm_pcie_setup()
1022 /* PCIe->SCB endian mode for BAR */ in brcm_pcie_setup()
1036 return 0; in brcm_pcie_setup()
1039 /* L23 is a low-power PCIe link state */
1040 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1042 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1054 for (i = 0; i < 15 && !l23; i++) { in brcm_pcie_enter_l23()
1062 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1065 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1075 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1076 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1077 u32 tmp, combined_mask = 0; in brcm_phy_cntl()
1079 void __iomem *base = pcie->base; in brcm_phy_cntl()
1082 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1083 val = start ? BIT_MASK(shifts[i]) : 0; in brcm_phy_cntl()
1092 val = start ? combined_mask : 0; in brcm_phy_cntl()
1094 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1096 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1101 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1103 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1106 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1108 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1111 static void brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1113 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1116 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1117 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1119 pcie->perst_set(pcie, 1); in brcm_pcie_turn_off()
1123 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK); in brcm_pcie_turn_off()
1131 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1132 pcie->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1137 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend() local
1140 brcm_pcie_turn_off(pcie); in brcm_pcie_suspend()
1141 ret = brcm_phy_stop(pcie); in brcm_pcie_suspend()
1142 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend()
1149 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume() local
1154 base = pcie->base; in brcm_pcie_resume()
1155 clk_prepare_enable(pcie->clk); in brcm_pcie_resume()
1157 ret = brcm_phy_start(pcie); in brcm_pcie_resume()
1162 pcie->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume()
1164 /* SERDES_IDDQ = 0 */ in brcm_pcie_resume()
1166 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK); in brcm_pcie_resume()
1172 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume()
1176 if (pcie->msi) in brcm_pcie_resume()
1177 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume()
1179 return 0; in brcm_pcie_resume()
1182 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume()
1186 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1188 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1189 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1190 brcm_phy_stop(pcie); in __brcm_pcie_remove()
1191 reset_control_assert(pcie->rescal); in __brcm_pcie_remove()
1192 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1197 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1198 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1200 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1201 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1202 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1204 return 0; in brcm_pcie_remove()
1208 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1209 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1210 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1211 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1212 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1218 struct device_node *np = pdev->dev.of_node, *msi_np; in brcm_pcie_probe()
1221 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1224 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1226 return -ENOMEM; in brcm_pcie_probe()
1228 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1231 return -EINVAL; in brcm_pcie_probe()
1234 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1235 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1236 pcie->np = np; in brcm_pcie_probe()
1237 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
1238 pcie->type = data->type; in brcm_pcie_probe()
1239 pcie->perst_set = data->perst_set; in brcm_pcie_probe()
1240 pcie->bridge_sw_init_set = data->bridge_sw_init_set; in brcm_pcie_probe()
1242 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1243 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1244 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1246 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1247 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1248 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1251 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1253 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1255 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1257 dev_err(&pdev->dev, "could not enable clock\n"); in brcm_pcie_probe()
1260 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1261 if (IS_ERR(pcie->rescal)) { in brcm_pcie_probe()
1262 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1263 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1266 ret = reset_control_deassert(pcie->rescal); in brcm_pcie_probe()
1268 dev_err(&pdev->dev, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1270 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1272 reset_control_assert(pcie->rescal); in brcm_pcie_probe()
1273 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1277 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1281 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1283 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1284 if (pci_msi_enabled() && msi_np == pcie->np) { in brcm_pcie_probe()
1285 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1287 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1292 bridge->ops = &brcm_pcie_ops; in brcm_pcie_probe()
1293 bridge->sysdata = pcie; in brcm_pcie_probe()
1295 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1299 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1314 .name = "brcm-pcie",
1322 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");