Lines Matching +full:port +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
36 /* PCIe per port registers */
72 /* PCIe V2 per-port registers */
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
143 * struct mtk_pcie_soc - differentiate between host generations
156 int (*startup)(struct mtk_pcie_port *port);
157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
161 * struct mtk_pcie_port - PCIe port information
162 * @base: IO mapped register base
163 * @list: port list
165 * @reset: pointer to port reset control
175 * @slot: port slot
184 void __iomem *base; member
205 * struct mtk_pcie - PCIe host information
207 * @base: IO mapped register base
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
210 * @ports: pointer to PCIe port information
211 * @soc: pointer to SoC-dependent operations
215 void __iomem *base; member
224 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerdown()
226 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_subsys_powerdown()
232 static void mtk_pcie_port_free(struct mtk_pcie_port *port) in mtk_pcie_port_free() argument
234 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_port_free()
235 struct device *dev = pcie->dev; in mtk_pcie_port_free()
237 devm_iounmap(dev, port->base); in mtk_pcie_port_free()
238 list_del(&port->list); in mtk_pcie_port_free()
239 devm_kfree(dev, port); in mtk_pcie_port_free()
244 struct mtk_pcie_port *port, *tmp; in mtk_pcie_put_resources() local
246 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_put_resources()
247 phy_power_off(port->phy); in mtk_pcie_put_resources()
248 phy_exit(port->phy); in mtk_pcie_put_resources()
249 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_put_resources()
250 clk_disable_unprepare(port->obff_ck); in mtk_pcie_put_resources()
251 clk_disable_unprepare(port->axi_ck); in mtk_pcie_put_resources()
252 clk_disable_unprepare(port->aux_ck); in mtk_pcie_put_resources()
253 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_put_resources()
254 clk_disable_unprepare(port->sys_ck); in mtk_pcie_put_resources()
255 mtk_pcie_port_free(port); in mtk_pcie_put_resources()
261 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port) in mtk_pcie_check_cfg_cpld() argument
266 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val, in mtk_pcie_check_cfg_cpld()
272 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS) in mtk_pcie_check_cfg_cpld()
278 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, in mtk_pcie_hw_rd_cfg() argument
285 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_rd_cfg()
286 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_rd_cfg()
288 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_rd_cfg()
291 tmp = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
293 writel(tmp, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_rd_cfg()
296 if (mtk_pcie_check_cfg_cpld(port)) in mtk_pcie_hw_rd_cfg()
300 *val = readl(port->base + PCIE_CFG_RDATA); in mtk_pcie_hw_rd_cfg()
310 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn, in mtk_pcie_hw_wr_cfg() argument
315 port->base + PCIE_CFG_HEADER0); in mtk_pcie_hw_wr_cfg()
316 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1); in mtk_pcie_hw_wr_cfg()
318 port->base + PCIE_CFG_HEADER2); in mtk_pcie_hw_wr_cfg()
322 writel(val, port->base + PCIE_CFG_WDATA); in mtk_pcie_hw_wr_cfg()
325 val = readl(port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
327 writel(val, port->base + PCIE_APP_TLP_REQ); in mtk_pcie_hw_wr_cfg()
330 return mtk_pcie_check_cfg_cpld(port); in mtk_pcie_hw_wr_cfg()
336 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_find_port()
337 struct mtk_pcie_port *port; in mtk_pcie_find_port() local
342 * of the port in the root bus. in mtk_pcie_find_port()
344 while (bus && bus->number) { in mtk_pcie_find_port()
345 dev = bus->self; in mtk_pcie_find_port()
346 bus = dev->bus; in mtk_pcie_find_port()
347 devfn = dev->devfn; in mtk_pcie_find_port()
350 list_for_each_entry(port, &pcie->ports, list) in mtk_pcie_find_port()
351 if (port->slot == PCI_SLOT(devfn)) in mtk_pcie_find_port()
352 return port; in mtk_pcie_find_port()
360 struct mtk_pcie_port *port; in mtk_pcie_config_read() local
361 u32 bn = bus->number; in mtk_pcie_config_read()
364 port = mtk_pcie_find_port(bus, devfn); in mtk_pcie_config_read()
365 if (!port) { in mtk_pcie_config_read()
370 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val); in mtk_pcie_config_read()
380 struct mtk_pcie_port *port; in mtk_pcie_config_write() local
381 u32 bn = bus->number; in mtk_pcie_config_write()
383 port = mtk_pcie_find_port(bus, devfn); in mtk_pcie_config_write()
384 if (!port) in mtk_pcie_config_write()
387 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val); in mtk_pcie_config_write()
397 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); in mtk_compose_msi_msg() local
400 /* MT2712/MT7622 only support 32-bit MSI addresses */ in mtk_compose_msi_msg()
401 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_compose_msi_msg()
402 msg->address_hi = 0; in mtk_compose_msi_msg()
403 msg->address_lo = lower_32_bits(addr); in mtk_compose_msi_msg()
405 msg->data = data->hwirq; in mtk_compose_msi_msg()
407 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n", in mtk_compose_msi_msg()
408 (int)data->hwirq, msg->address_hi, msg->address_lo); in mtk_compose_msi_msg()
414 return -EINVAL; in mtk_msi_set_affinity()
419 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); in mtk_msi_ack_irq() local
420 u32 hwirq = data->hwirq; in mtk_msi_ack_irq()
422 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS); in mtk_msi_ack_irq()
435 struct mtk_pcie_port *port = domain->host_data; in mtk_pcie_irq_domain_alloc() local
439 mutex_lock(&port->lock); in mtk_pcie_irq_domain_alloc()
441 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM); in mtk_pcie_irq_domain_alloc()
443 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
444 return -ENOSPC; in mtk_pcie_irq_domain_alloc()
447 __set_bit(bit, port->msi_irq_in_use); in mtk_pcie_irq_domain_alloc()
449 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_alloc()
452 domain->host_data, handle_edge_irq, in mtk_pcie_irq_domain_alloc()
462 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d); in mtk_pcie_irq_domain_free() local
464 mutex_lock(&port->lock); in mtk_pcie_irq_domain_free()
466 if (!test_bit(d->hwirq, port->msi_irq_in_use)) in mtk_pcie_irq_domain_free()
467 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n", in mtk_pcie_irq_domain_free()
468 d->hwirq); in mtk_pcie_irq_domain_free()
470 __clear_bit(d->hwirq, port->msi_irq_in_use); in mtk_pcie_irq_domain_free()
472 mutex_unlock(&port->lock); in mtk_pcie_irq_domain_free()
495 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port) in mtk_pcie_allocate_msi_domains() argument
497 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node); in mtk_pcie_allocate_msi_domains()
499 mutex_init(&port->lock); in mtk_pcie_allocate_msi_domains()
501 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM, in mtk_pcie_allocate_msi_domains()
502 &msi_domain_ops, port); in mtk_pcie_allocate_msi_domains()
503 if (!port->inner_domain) { in mtk_pcie_allocate_msi_domains()
504 dev_err(port->pcie->dev, "failed to create IRQ domain\n"); in mtk_pcie_allocate_msi_domains()
505 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
508 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info, in mtk_pcie_allocate_msi_domains()
509 port->inner_domain); in mtk_pcie_allocate_msi_domains()
510 if (!port->msi_domain) { in mtk_pcie_allocate_msi_domains()
511 dev_err(port->pcie->dev, "failed to create MSI domain\n"); in mtk_pcie_allocate_msi_domains()
512 irq_domain_remove(port->inner_domain); in mtk_pcie_allocate_msi_domains()
513 return -ENOMEM; in mtk_pcie_allocate_msi_domains()
519 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) in mtk_pcie_enable_msi() argument
524 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR); in mtk_pcie_enable_msi()
526 writel(val, port->base + PCIE_IMSI_ADDR); in mtk_pcie_enable_msi()
528 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
530 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_enable_msi()
535 struct mtk_pcie_port *port, *tmp; in mtk_pcie_irq_teardown() local
537 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { in mtk_pcie_irq_teardown()
538 irq_set_chained_handler_and_data(port->irq, NULL, NULL); in mtk_pcie_irq_teardown()
540 if (port->irq_domain) in mtk_pcie_irq_teardown()
541 irq_domain_remove(port->irq_domain); in mtk_pcie_irq_teardown()
544 if (port->msi_domain) in mtk_pcie_irq_teardown()
545 irq_domain_remove(port->msi_domain); in mtk_pcie_irq_teardown()
546 if (port->inner_domain) in mtk_pcie_irq_teardown()
547 irq_domain_remove(port->inner_domain); in mtk_pcie_irq_teardown()
550 irq_dispose_mapping(port->irq); in mtk_pcie_irq_teardown()
558 irq_set_chip_data(irq, domain->host_data); in mtk_pcie_intx_map()
567 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port, in mtk_pcie_init_irq_domain() argument
570 struct device *dev = port->pcie->dev; in mtk_pcie_init_irq_domain()
578 return -ENODEV; in mtk_pcie_init_irq_domain()
581 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX, in mtk_pcie_init_irq_domain()
582 &intx_domain_ops, port); in mtk_pcie_init_irq_domain()
584 if (!port->irq_domain) { in mtk_pcie_init_irq_domain()
586 return -ENODEV; in mtk_pcie_init_irq_domain()
590 ret = mtk_pcie_allocate_msi_domains(port); in mtk_pcie_init_irq_domain()
600 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); in mtk_pcie_intr_handler() local
608 status = readl(port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
612 writel(1 << bit, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
613 virq = irq_find_mapping(port->irq_domain, in mtk_pcie_intr_handler()
614 bit - INTX_SHIFT); in mtk_pcie_intr_handler()
626 * edge-triggered interrupt type, its status should in mtk_pcie_intr_handler()
630 writel(MSI_STATUS, port->base + PCIE_INT_STATUS); in mtk_pcie_intr_handler()
631 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) { in mtk_pcie_intr_handler()
633 virq = irq_find_mapping(port->inner_domain, bit); in mtk_pcie_intr_handler()
643 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port, in mtk_pcie_setup_irq() argument
646 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_setup_irq()
647 struct device *dev = pcie->dev; in mtk_pcie_setup_irq()
651 err = mtk_pcie_init_irq_domain(port, node); in mtk_pcie_setup_irq()
657 port->irq = platform_get_irq(pdev, port->slot); in mtk_pcie_setup_irq()
658 if (port->irq < 0) in mtk_pcie_setup_irq()
659 return port->irq; in mtk_pcie_setup_irq()
661 irq_set_chained_handler_and_data(port->irq, in mtk_pcie_setup_irq()
662 mtk_pcie_intr_handler, port); in mtk_pcie_setup_irq()
667 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) in mtk_pcie_startup_port_v2() argument
669 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port_v2()
673 const struct mtk_pcie_soc *soc = port->pcie->soc; in mtk_pcie_startup_port_v2()
677 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM); in mtk_pcie_startup_port_v2()
679 mem = entry->res; in mtk_pcie_startup_port_v2()
681 return -EINVAL; in mtk_pcie_startup_port_v2()
684 if (pcie->base) { in mtk_pcie_startup_port_v2()
685 val = readl(pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
686 val |= PCIE_CSR_LTSSM_EN(port->slot) | in mtk_pcie_startup_port_v2()
687 PCIE_CSR_ASPM_L1_EN(port->slot); in mtk_pcie_startup_port_v2()
688 writel(val, pcie->base + PCIE_SYS_CFG_V2); in mtk_pcie_startup_port_v2()
692 writel(0, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
699 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
701 /* De-assert PHY, PE, PIPE, MAC and configuration reset */ in mtk_pcie_startup_port_v2()
702 val = readl(port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
705 writel(val, port->base + PCIE_RST_CTRL); in mtk_pcie_startup_port_v2()
708 if (soc->need_fix_class_id) { in mtk_pcie_startup_port_v2()
710 writew(val, port->base + PCIE_CONF_VEND_ID); in mtk_pcie_startup_port_v2()
713 writew(val, port->base + PCIE_CONF_CLASS_ID); in mtk_pcie_startup_port_v2()
716 if (soc->need_fix_device_id) in mtk_pcie_startup_port_v2()
717 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID); in mtk_pcie_startup_port_v2()
720 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val, in mtk_pcie_startup_port_v2()
724 return -ETIMEDOUT; in mtk_pcie_startup_port_v2()
727 val = readl(port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
729 writel(val, port->base + PCIE_INT_MASK); in mtk_pcie_startup_port_v2()
732 mtk_pcie_enable_msi(port); in mtk_pcie_startup_port_v2()
735 val = lower_32_bits(mem->start) | in mtk_pcie_startup_port_v2()
737 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L); in mtk_pcie_startup_port_v2()
739 val = upper_32_bits(mem->start); in mtk_pcie_startup_port_v2()
740 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H); in mtk_pcie_startup_port_v2()
744 writel(val, port->base + PCIE_AXI_WINDOW0); in mtk_pcie_startup_port_v2()
752 struct mtk_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus()
755 bus->number), pcie->base + PCIE_CFG_ADDR); in mtk_pcie_map_bus()
757 return pcie->base + PCIE_CFG_DATA + (where & 3); in mtk_pcie_map_bus()
766 static int mtk_pcie_startup_port(struct mtk_pcie_port *port) in mtk_pcie_startup_port() argument
768 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_startup_port()
769 u32 func = PCI_FUNC(port->slot << 3); in mtk_pcie_startup_port()
770 u32 slot = PCI_SLOT(port->slot << 3); in mtk_pcie_startup_port()
774 /* assert port PERST_N */ in mtk_pcie_startup_port()
775 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
776 val |= PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
777 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
779 /* de-assert port PERST_N */ in mtk_pcie_startup_port()
780 val = readl(pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
781 val &= ~PCIE_PORT_PERST(port->slot); in mtk_pcie_startup_port()
782 writel(val, pcie->base + PCIE_SYS_CFG); in mtk_pcie_startup_port()
785 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val, in mtk_pcie_startup_port()
789 return -ETIMEDOUT; in mtk_pcie_startup_port()
792 val = readl(pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
793 val |= PCIE_PORT_INT_EN(port->slot); in mtk_pcie_startup_port()
794 writel(val, pcie->base + PCIE_INT_ENABLE); in mtk_pcie_startup_port()
798 port->base + PCIE_BAR0_SETUP); in mtk_pcie_startup_port()
801 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS); in mtk_pcie_startup_port()
805 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
806 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
810 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
811 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
815 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
816 val = readl(pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
820 pcie->base + PCIE_CFG_ADDR); in mtk_pcie_startup_port()
821 writel(val, pcie->base + PCIE_CFG_DATA); in mtk_pcie_startup_port()
826 static void mtk_pcie_enable_port(struct mtk_pcie_port *port) in mtk_pcie_enable_port() argument
828 struct mtk_pcie *pcie = port->pcie; in mtk_pcie_enable_port()
829 struct device *dev = pcie->dev; in mtk_pcie_enable_port()
832 err = clk_prepare_enable(port->sys_ck); in mtk_pcie_enable_port()
834 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot); in mtk_pcie_enable_port()
838 err = clk_prepare_enable(port->ahb_ck); in mtk_pcie_enable_port()
840 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot); in mtk_pcie_enable_port()
844 err = clk_prepare_enable(port->aux_ck); in mtk_pcie_enable_port()
846 dev_err(dev, "failed to enable aux_ck%d\n", port->slot); in mtk_pcie_enable_port()
850 err = clk_prepare_enable(port->axi_ck); in mtk_pcie_enable_port()
852 dev_err(dev, "failed to enable axi_ck%d\n", port->slot); in mtk_pcie_enable_port()
856 err = clk_prepare_enable(port->obff_ck); in mtk_pcie_enable_port()
858 dev_err(dev, "failed to enable obff_ck%d\n", port->slot); in mtk_pcie_enable_port()
862 err = clk_prepare_enable(port->pipe_ck); in mtk_pcie_enable_port()
864 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot); in mtk_pcie_enable_port()
868 reset_control_assert(port->reset); in mtk_pcie_enable_port()
869 reset_control_deassert(port->reset); in mtk_pcie_enable_port()
871 err = phy_init(port->phy); in mtk_pcie_enable_port()
873 dev_err(dev, "failed to initialize port%d phy\n", port->slot); in mtk_pcie_enable_port()
877 err = phy_power_on(port->phy); in mtk_pcie_enable_port()
879 dev_err(dev, "failed to power on port%d phy\n", port->slot); in mtk_pcie_enable_port()
883 if (!pcie->soc->startup(port)) in mtk_pcie_enable_port()
886 dev_info(dev, "Port%d link down\n", port->slot); in mtk_pcie_enable_port()
888 phy_power_off(port->phy); in mtk_pcie_enable_port()
890 phy_exit(port->phy); in mtk_pcie_enable_port()
892 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_enable_port()
894 clk_disable_unprepare(port->obff_ck); in mtk_pcie_enable_port()
896 clk_disable_unprepare(port->axi_ck); in mtk_pcie_enable_port()
898 clk_disable_unprepare(port->aux_ck); in mtk_pcie_enable_port()
900 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_enable_port()
902 clk_disable_unprepare(port->sys_ck); in mtk_pcie_enable_port()
904 mtk_pcie_port_free(port); in mtk_pcie_enable_port()
911 struct mtk_pcie_port *port; in mtk_pcie_parse_port() local
912 struct device *dev = pcie->dev; in mtk_pcie_parse_port()
917 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); in mtk_pcie_parse_port()
918 if (!port) in mtk_pcie_parse_port()
919 return -ENOMEM; in mtk_pcie_parse_port()
921 snprintf(name, sizeof(name), "port%d", slot); in mtk_pcie_parse_port()
922 port->base = devm_platform_ioremap_resource_byname(pdev, name); in mtk_pcie_parse_port()
923 if (IS_ERR(port->base)) { in mtk_pcie_parse_port()
924 dev_err(dev, "failed to map port%d base\n", slot); in mtk_pcie_parse_port()
925 return PTR_ERR(port->base); in mtk_pcie_parse_port()
929 port->sys_ck = devm_clk_get(dev, name); in mtk_pcie_parse_port()
930 if (IS_ERR(port->sys_ck)) { in mtk_pcie_parse_port()
932 return PTR_ERR(port->sys_ck); in mtk_pcie_parse_port()
937 port->ahb_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
938 if (IS_ERR(port->ahb_ck)) in mtk_pcie_parse_port()
939 return PTR_ERR(port->ahb_ck); in mtk_pcie_parse_port()
942 port->axi_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
943 if (IS_ERR(port->axi_ck)) in mtk_pcie_parse_port()
944 return PTR_ERR(port->axi_ck); in mtk_pcie_parse_port()
947 port->aux_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
948 if (IS_ERR(port->aux_ck)) in mtk_pcie_parse_port()
949 return PTR_ERR(port->aux_ck); in mtk_pcie_parse_port()
952 port->obff_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
953 if (IS_ERR(port->obff_ck)) in mtk_pcie_parse_port()
954 return PTR_ERR(port->obff_ck); in mtk_pcie_parse_port()
957 port->pipe_ck = devm_clk_get_optional(dev, name); in mtk_pcie_parse_port()
958 if (IS_ERR(port->pipe_ck)) in mtk_pcie_parse_port()
959 return PTR_ERR(port->pipe_ck); in mtk_pcie_parse_port()
961 snprintf(name, sizeof(name), "pcie-rst%d", slot); in mtk_pcie_parse_port()
962 port->reset = devm_reset_control_get_optional_exclusive(dev, name); in mtk_pcie_parse_port()
963 if (PTR_ERR(port->reset) == -EPROBE_DEFER) in mtk_pcie_parse_port()
964 return PTR_ERR(port->reset); in mtk_pcie_parse_port()
967 snprintf(name, sizeof(name), "pcie-phy%d", slot); in mtk_pcie_parse_port()
968 port->phy = devm_phy_optional_get(dev, name); in mtk_pcie_parse_port()
969 if (IS_ERR(port->phy)) in mtk_pcie_parse_port()
970 return PTR_ERR(port->phy); in mtk_pcie_parse_port()
972 port->slot = slot; in mtk_pcie_parse_port()
973 port->pcie = pcie; in mtk_pcie_parse_port()
975 if (pcie->soc->setup_irq) { in mtk_pcie_parse_port()
976 err = pcie->soc->setup_irq(port, node); in mtk_pcie_parse_port()
981 INIT_LIST_HEAD(&port->list); in mtk_pcie_parse_port()
982 list_add_tail(&port->list, &pcie->ports); in mtk_pcie_parse_port()
989 struct device *dev = pcie->dev; in mtk_pcie_subsys_powerup()
997 pcie->base = devm_ioremap_resource(dev, regs); in mtk_pcie_subsys_powerup()
998 if (IS_ERR(pcie->base)) { in mtk_pcie_subsys_powerup()
1000 return PTR_ERR(pcie->base); in mtk_pcie_subsys_powerup()
1004 pcie->free_ck = devm_clk_get(dev, "free_ck"); in mtk_pcie_subsys_powerup()
1005 if (IS_ERR(pcie->free_ck)) { in mtk_pcie_subsys_powerup()
1006 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER) in mtk_pcie_subsys_powerup()
1007 return -EPROBE_DEFER; in mtk_pcie_subsys_powerup()
1009 pcie->free_ck = NULL; in mtk_pcie_subsys_powerup()
1016 err = clk_prepare_enable(pcie->free_ck); in mtk_pcie_subsys_powerup()
1033 struct device *dev = pcie->dev; in mtk_pcie_setup()
1034 struct device_node *node = dev->of_node, *child; in mtk_pcie_setup()
1035 struct mtk_pcie_port *port, *tmp; in mtk_pcie_setup() local
1058 /* enable each port, and then check link status */ in mtk_pcie_setup()
1059 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_setup()
1060 mtk_pcie_enable_port(port); in mtk_pcie_setup()
1063 if (list_empty(&pcie->ports)) in mtk_pcie_setup()
1074 struct device *dev = &pdev->dev; in mtk_pcie_probe()
1081 return -ENOMEM; in mtk_pcie_probe()
1085 pcie->dev = dev; in mtk_pcie_probe()
1086 pcie->soc = of_device_get_match_data(dev); in mtk_pcie_probe()
1088 INIT_LIST_HEAD(&pcie->ports); in mtk_pcie_probe()
1094 host->ops = pcie->soc->ops; in mtk_pcie_probe()
1095 host->sysdata = pcie; in mtk_pcie_probe()
1104 if (!list_empty(&pcie->ports)) in mtk_pcie_probe()
1114 struct list_head *windows = &host->windows; in mtk_pcie_free_resources()
1124 pci_stop_root_bus(host->bus); in mtk_pcie_remove()
1125 pci_remove_root_bus(host->bus); in mtk_pcie_remove()
1138 struct mtk_pcie_port *port; in mtk_pcie_suspend_noirq() local
1140 if (list_empty(&pcie->ports)) in mtk_pcie_suspend_noirq()
1143 list_for_each_entry(port, &pcie->ports, list) { in mtk_pcie_suspend_noirq()
1144 clk_disable_unprepare(port->pipe_ck); in mtk_pcie_suspend_noirq()
1145 clk_disable_unprepare(port->obff_ck); in mtk_pcie_suspend_noirq()
1146 clk_disable_unprepare(port->axi_ck); in mtk_pcie_suspend_noirq()
1147 clk_disable_unprepare(port->aux_ck); in mtk_pcie_suspend_noirq()
1148 clk_disable_unprepare(port->ahb_ck); in mtk_pcie_suspend_noirq()
1149 clk_disable_unprepare(port->sys_ck); in mtk_pcie_suspend_noirq()
1150 phy_power_off(port->phy); in mtk_pcie_suspend_noirq()
1151 phy_exit(port->phy); in mtk_pcie_suspend_noirq()
1154 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_suspend_noirq()
1162 struct mtk_pcie_port *port, *tmp; in mtk_pcie_resume_noirq() local
1164 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1167 clk_prepare_enable(pcie->free_ck); in mtk_pcie_resume_noirq()
1169 list_for_each_entry_safe(port, tmp, &pcie->ports, list) in mtk_pcie_resume_noirq()
1170 mtk_pcie_enable_port(port); in mtk_pcie_resume_noirq()
1173 if (list_empty(&pcie->ports)) in mtk_pcie_resume_noirq()
1174 clk_disable_unprepare(pcie->free_ck); in mtk_pcie_resume_noirq()
1212 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1213 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1214 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1215 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1216 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1224 .name = "mtk-pcie",