Lines Matching +full:pcie +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
3 * PCIe host controller driver for NWL PCIe Bridge
4 * Based on pcie-xilinx.c, pci-tegra.c
6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
28 #define BRCFG_PCIE_RX0 0x00000000
29 #define BRCFG_INTERRUPT 0x00000010
30 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
32 /* Egress - Bridge translation registers */
33 #define E_BREG_CAPABILITIES 0x00000200
34 #define E_BREG_CONTROL 0x00000208
35 #define E_BREG_BASE_LO 0x00000210
36 #define E_BREG_BASE_HI 0x00000214
37 #define E_ECAM_CAPABILITIES 0x00000220
38 #define E_ECAM_CONTROL 0x00000228
39 #define E_ECAM_BASE_LO 0x00000230
40 #define E_ECAM_BASE_HI 0x00000234
42 /* Ingress - address translations */
43 #define I_MSII_CAPABILITIES 0x00000300
44 #define I_MSII_CONTROL 0x00000308
45 #define I_MSII_BASE_LO 0x00000310
46 #define I_MSII_BASE_HI 0x00000314
48 #define I_ISUB_CONTROL 0x000003E8
49 #define SET_ISUB_CONTROL BIT(0)
50 /* Rxed msg fifo - Interrupt status registers */
51 #define MSGF_MISC_STATUS 0x00000400
52 #define MSGF_MISC_MASK 0x00000404
53 #define MSGF_LEG_STATUS 0x00000420
54 #define MSGF_LEG_MASK 0x00000424
55 #define MSGF_MSI_STATUS_LO 0x00000440
56 #define MSGF_MSI_STATUS_HI 0x00000444
57 #define MSGF_MSI_MASK_LO 0x00000448
58 #define MSGF_MSI_MASK_HI 0x0000044C
69 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
102 #define MSGF_LEG_SR_INTA BIT(0)
110 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
111 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
113 #define MSII_PRESENT BIT(0)
114 #define MSII_ENABLE BIT(0)
118 #define BRCFG_INTERRUPT_MASK BIT(0)
119 #define BREG_PRESENT BIT(0)
120 #define BREG_ENABLE BIT(0)
124 #define E_ECAM_PRESENT BIT(0)
125 #define E_ECAM_CR_ENABLE BIT(0)
132 #define CFG_DMA_REG_BAR GENMASK(2, 0)
137 #define PS_LINKUP_OFFSET 0x00000238
138 #define PCIE_PHY_LINKUP_BIT BIT(0)
161 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
176 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
178 return readl(pcie->breg_base + off); in nwl_bridge_readl()
181 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
183 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
186 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
188 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
193 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
195 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
200 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
202 struct device *dev = pcie->dev; in nwl_wait_for_link()
206 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { in nwl_wait_for_link()
207 if (nwl_phy_link_up(pcie)) in nwl_wait_for_link()
208 return 0; in nwl_wait_for_link()
213 return -ETIMEDOUT; in nwl_wait_for_link()
218 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_valid_device() local
222 if (!nwl_pcie_link_up(pcie)) in nwl_pcie_valid_device()
224 } else if (devfn > 0) in nwl_pcie_valid_device()
232 * nwl_pcie_map_bus - Get configuration base
244 struct nwl_pcie *pcie = bus->sysdata; in nwl_pcie_map_bus() local
250 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) | in nwl_pcie_map_bus()
253 return pcie->ecam_base + relbus + where; in nwl_pcie_map_bus()
256 /* PCIe operations */
265 struct nwl_pcie *pcie = data; in nwl_pcie_misc_handler() local
266 struct device *dev = pcie->dev; in nwl_pcie_misc_handler()
270 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_misc_handler()
294 dev_err(dev, "Non-Fatal Error in AER Capability\n"); in nwl_pcie_misc_handler()
303 dev_err(dev, "Non-Fatal Error Detected\n"); in nwl_pcie_misc_handler()
315 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS); in nwl_pcie_misc_handler()
323 struct nwl_pcie *pcie; in nwl_pcie_leg_handler() local
329 pcie = irq_desc_get_handler_data(desc); in nwl_pcie_leg_handler()
331 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_leg_handler()
332 MSGF_LEG_SR_MASKALL) != 0) { in nwl_pcie_leg_handler()
334 virq = irq_find_mapping(pcie->legacy_irq_domain, bit); in nwl_pcie_leg_handler()
343 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg) in nwl_pcie_handle_msi_irq() argument
350 msi = &pcie->msi; in nwl_pcie_handle_msi_irq()
352 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) { in nwl_pcie_handle_msi_irq()
354 nwl_bridge_writel(pcie, 1 << bit, status_reg); in nwl_pcie_handle_msi_irq()
355 virq = irq_find_mapping(msi->dev_domain, bit); in nwl_pcie_handle_msi_irq()
365 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_high() local
368 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI); in nwl_pcie_msi_handler_high()
375 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc); in nwl_pcie_msi_handler_low() local
378 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO); in nwl_pcie_msi_handler_low()
384 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_mask_leg_irq()
385 struct nwl_pcie *pcie; in nwl_mask_leg_irq() local
390 pcie = irq_desc_get_chip_data(desc); in nwl_mask_leg_irq()
391 mask = 1 << (data->hwirq - 1); in nwl_mask_leg_irq()
392 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
393 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_mask_leg_irq()
394 nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK); in nwl_mask_leg_irq()
395 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_mask_leg_irq()
400 struct irq_desc *desc = irq_to_desc(data->irq); in nwl_unmask_leg_irq()
401 struct nwl_pcie *pcie; in nwl_unmask_leg_irq() local
406 pcie = irq_desc_get_chip_data(desc); in nwl_unmask_leg_irq()
407 mask = 1 << (data->hwirq - 1); in nwl_unmask_leg_irq()
408 raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
409 val = nwl_bridge_readl(pcie, MSGF_LEG_MASK); in nwl_unmask_leg_irq()
410 nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK); in nwl_unmask_leg_irq()
411 raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags); in nwl_unmask_leg_irq()
426 irq_set_chip_data(irq, domain->host_data); in nwl_legacy_map()
429 return 0; in nwl_legacy_map()
455 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_compose_msi_msg() local
456 phys_addr_t msi_addr = pcie->phys_pcie_reg_base; in nwl_compose_msi_msg()
458 msg->address_lo = lower_32_bits(msi_addr); in nwl_compose_msi_msg()
459 msg->address_hi = upper_32_bits(msi_addr); in nwl_compose_msi_msg()
460 msg->data = data->hwirq; in nwl_compose_msi_msg()
466 return -EINVAL; in nwl_msi_set_affinity()
478 struct nwl_pcie *pcie = domain->host_data; in nwl_irq_domain_alloc() local
479 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_alloc()
483 mutex_lock(&msi->lock); in nwl_irq_domain_alloc()
484 bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR, in nwl_irq_domain_alloc()
486 if (bit < 0) { in nwl_irq_domain_alloc()
487 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
488 return -ENOSPC; in nwl_irq_domain_alloc()
491 for (i = 0; i < nr_irqs; i++) { in nwl_irq_domain_alloc()
493 domain->host_data, handle_simple_irq, in nwl_irq_domain_alloc()
496 mutex_unlock(&msi->lock); in nwl_irq_domain_alloc()
497 return 0; in nwl_irq_domain_alloc()
504 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data); in nwl_irq_domain_free() local
505 struct nwl_msi *msi = &pcie->msi; in nwl_irq_domain_free()
507 mutex_lock(&msi->lock); in nwl_irq_domain_free()
508 bitmap_release_region(msi->bitmap, data->hwirq, in nwl_irq_domain_free()
510 mutex_unlock(&msi->lock); in nwl_irq_domain_free()
518 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_msi_irq_domain() argument
521 struct device *dev = pcie->dev; in nwl_pcie_init_msi_irq_domain()
522 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node); in nwl_pcie_init_msi_irq_domain()
523 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_init_msi_irq_domain()
525 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR, in nwl_pcie_init_msi_irq_domain()
526 &dev_msi_domain_ops, pcie); in nwl_pcie_init_msi_irq_domain()
527 if (!msi->dev_domain) { in nwl_pcie_init_msi_irq_domain()
529 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
531 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in nwl_pcie_init_msi_irq_domain()
533 msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
534 if (!msi->msi_domain) { in nwl_pcie_init_msi_irq_domain()
536 irq_domain_remove(msi->dev_domain); in nwl_pcie_init_msi_irq_domain()
537 return -ENOMEM; in nwl_pcie_init_msi_irq_domain()
540 return 0; in nwl_pcie_init_msi_irq_domain()
543 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie) in nwl_pcie_init_irq_domain() argument
545 struct device *dev = pcie->dev; in nwl_pcie_init_irq_domain()
546 struct device_node *node = dev->of_node; in nwl_pcie_init_irq_domain()
552 return -EINVAL; in nwl_pcie_init_irq_domain()
555 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node, in nwl_pcie_init_irq_domain()
558 pcie); in nwl_pcie_init_irq_domain()
560 if (!pcie->legacy_irq_domain) { in nwl_pcie_init_irq_domain()
562 return -ENOMEM; in nwl_pcie_init_irq_domain()
565 raw_spin_lock_init(&pcie->leg_mask_lock); in nwl_pcie_init_irq_domain()
566 nwl_pcie_init_msi_irq_domain(pcie); in nwl_pcie_init_irq_domain()
567 return 0; in nwl_pcie_init_irq_domain()
570 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie) in nwl_pcie_enable_msi() argument
572 struct device *dev = pcie->dev; in nwl_pcie_enable_msi()
574 struct nwl_msi *msi = &pcie->msi; in nwl_pcie_enable_msi()
579 mutex_init(&msi->lock); in nwl_pcie_enable_msi()
581 msi->bitmap = kzalloc(size, GFP_KERNEL); in nwl_pcie_enable_msi()
582 if (!msi->bitmap) in nwl_pcie_enable_msi()
583 return -ENOMEM; in nwl_pcie_enable_msi()
586 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1"); in nwl_pcie_enable_msi()
587 if (msi->irq_msi1 < 0) { in nwl_pcie_enable_msi()
588 ret = -EINVAL; in nwl_pcie_enable_msi()
592 irq_set_chained_handler_and_data(msi->irq_msi1, in nwl_pcie_enable_msi()
593 nwl_pcie_msi_handler_high, pcie); in nwl_pcie_enable_msi()
596 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0"); in nwl_pcie_enable_msi()
597 if (msi->irq_msi0 < 0) { in nwl_pcie_enable_msi()
598 ret = -EINVAL; in nwl_pcie_enable_msi()
602 irq_set_chained_handler_and_data(msi->irq_msi0, in nwl_pcie_enable_msi()
603 nwl_pcie_msi_handler_low, pcie); in nwl_pcie_enable_msi()
606 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT; in nwl_pcie_enable_msi()
609 ret = -EIO; in nwl_pcie_enable_msi()
614 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
618 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) | in nwl_pcie_enable_msi()
622 base = pcie->phys_pcie_reg_base; in nwl_pcie_enable_msi()
623 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO); in nwl_pcie_enable_msi()
624 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI); in nwl_pcie_enable_msi()
630 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
632 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) & in nwl_pcie_enable_msi()
635 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI); in nwl_pcie_enable_msi()
641 nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
643 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) & in nwl_pcie_enable_msi()
646 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO); in nwl_pcie_enable_msi()
648 return 0; in nwl_pcie_enable_msi()
650 kfree(msi->bitmap); in nwl_pcie_enable_msi()
651 msi->bitmap = NULL; in nwl_pcie_enable_msi()
655 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) in nwl_pcie_bridge_init() argument
657 struct device *dev = pcie->dev; in nwl_pcie_bridge_init()
659 u32 breg_val, ecam_val, first_busno = 0; in nwl_pcie_bridge_init()
662 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; in nwl_pcie_bridge_init()
669 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
671 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), in nwl_pcie_bridge_init()
675 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, in nwl_pcie_bridge_init()
679 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | in nwl_pcie_bridge_init()
683 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); in nwl_pcie_bridge_init()
686 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, in nwl_pcie_bridge_init()
689 err = nwl_wait_for_link(pcie); in nwl_pcie_bridge_init()
693 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; in nwl_pcie_bridge_init()
700 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
703 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | in nwl_pcie_bridge_init()
704 (pcie->ecam_value << E_ECAM_SIZE_SHIFT), in nwl_pcie_bridge_init()
707 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
709 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), in nwl_pcie_bridge_init()
713 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); in nwl_pcie_bridge_init()
714 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; in nwl_pcie_bridge_init()
718 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); in nwl_pcie_bridge_init()
719 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); in nwl_pcie_bridge_init()
721 if (nwl_pcie_link_up(pcie)) in nwl_pcie_bridge_init()
727 pcie->irq_misc = platform_get_irq_byname(pdev, "misc"); in nwl_pcie_bridge_init()
728 if (pcie->irq_misc < 0) in nwl_pcie_bridge_init()
729 return -EINVAL; in nwl_pcie_bridge_init()
731 err = devm_request_irq(dev, pcie->irq_misc, in nwl_pcie_bridge_init()
733 "nwl_pcie:misc", pcie); in nwl_pcie_bridge_init()
736 pcie->irq_misc); in nwl_pcie_bridge_init()
741 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
744 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & in nwl_pcie_bridge_init()
748 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); in nwl_pcie_bridge_init()
752 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
755 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & in nwl_pcie_bridge_init()
759 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); in nwl_pcie_bridge_init()
762 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) | in nwl_pcie_bridge_init()
765 return 0; in nwl_pcie_bridge_init()
768 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie, in nwl_pcie_parse_dt() argument
771 struct device *dev = pcie->dev; in nwl_pcie_parse_dt()
775 pcie->breg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
776 if (IS_ERR(pcie->breg_base)) in nwl_pcie_parse_dt()
777 return PTR_ERR(pcie->breg_base); in nwl_pcie_parse_dt()
778 pcie->phys_breg_base = res->start; in nwl_pcie_parse_dt()
781 pcie->pcireg_base = devm_ioremap_resource(dev, res); in nwl_pcie_parse_dt()
782 if (IS_ERR(pcie->pcireg_base)) in nwl_pcie_parse_dt()
783 return PTR_ERR(pcie->pcireg_base); in nwl_pcie_parse_dt()
784 pcie->phys_pcie_reg_base = res->start; in nwl_pcie_parse_dt()
787 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res); in nwl_pcie_parse_dt()
788 if (IS_ERR(pcie->ecam_base)) in nwl_pcie_parse_dt()
789 return PTR_ERR(pcie->ecam_base); in nwl_pcie_parse_dt()
790 pcie->phys_ecam_base = res->start; in nwl_pcie_parse_dt()
793 pcie->irq_intx = platform_get_irq_byname(pdev, "intx"); in nwl_pcie_parse_dt()
794 if (pcie->irq_intx < 0) in nwl_pcie_parse_dt()
795 return pcie->irq_intx; in nwl_pcie_parse_dt()
797 irq_set_chained_handler_and_data(pcie->irq_intx, in nwl_pcie_parse_dt()
798 nwl_pcie_leg_handler, pcie); in nwl_pcie_parse_dt()
800 return 0; in nwl_pcie_parse_dt()
804 { .compatible = "xlnx,nwl-pcie-2.11", },
810 struct device *dev = &pdev->dev; in nwl_pcie_probe()
811 struct nwl_pcie *pcie; in nwl_pcie_probe() local
815 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); in nwl_pcie_probe()
817 return -ENODEV; in nwl_pcie_probe()
819 pcie = pci_host_bridge_priv(bridge); in nwl_pcie_probe()
821 pcie->dev = dev; in nwl_pcie_probe()
822 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; in nwl_pcie_probe()
824 err = nwl_pcie_parse_dt(pcie, pdev); in nwl_pcie_probe()
830 pcie->clk = devm_clk_get(dev, NULL); in nwl_pcie_probe()
831 if (IS_ERR(pcie->clk)) in nwl_pcie_probe()
832 return PTR_ERR(pcie->clk); in nwl_pcie_probe()
834 err = clk_prepare_enable(pcie->clk); in nwl_pcie_probe()
836 dev_err(dev, "can't enable PCIe ref clock\n"); in nwl_pcie_probe()
840 err = nwl_pcie_bridge_init(pcie); in nwl_pcie_probe()
846 err = nwl_pcie_init_irq_domain(pcie); in nwl_pcie_probe()
852 bridge->sysdata = pcie; in nwl_pcie_probe()
853 bridge->ops = &nwl_pcie_ops; in nwl_pcie_probe()
856 err = nwl_pcie_enable_msi(pcie); in nwl_pcie_probe()
857 if (err < 0) { in nwl_pcie_probe()
868 .name = "nwl-pcie",