169 static void start_int_poll_timer(struct controller *ctrl, int sec);
170 static int hpc_check_cmd_status(struct controller *ctrl);
172 static inline u8 shpc_readb(struct controller *ctrl, int reg)  in shpc_readb()  argument
174 	return readb(ctrl->creg + reg);  in shpc_readb()
177 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)  in shpc_writeb()  argument
179 	writeb(val, ctrl->creg + reg);  in shpc_writeb()
182 static inline u16 shpc_readw(struct controller *ctrl, int reg)  in shpc_readw()  argument
184 	return readw(ctrl->creg + reg);  in shpc_readw()
187 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)  in shpc_writew()  argument
189 	writew(val, ctrl->creg + reg);  in shpc_writew()
192 static inline u32 shpc_readl(struct controller *ctrl, int reg)  in shpc_readl()  argument
194 	return readl(ctrl->creg + reg);  in shpc_readl()
197 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)  in shpc_writel()  argument
199 	writel(val, ctrl->creg + reg);  in shpc_writel()
202 static inline int shpc_indirect_read(struct controller *ctrl, int index,  in shpc_indirect_read()  argument
206 	u32 cap_offset = ctrl->cap_offset;  in shpc_indirect_read()
207 	struct pci_dev *pdev = ctrl->pci_dev;  in shpc_indirect_read()
220 	struct controller *ctrl = from_timer(ctrl, t, poll_timer);  in int_poll_timeout()  local
223 	shpc_isr(0, ctrl);  in int_poll_timeout()
228 	start_int_poll_timer(ctrl, shpchp_poll_time);  in int_poll_timeout()
234 static void start_int_poll_timer(struct controller *ctrl, int sec)  in start_int_poll_timer()  argument
240 	ctrl->poll_timer.expires = jiffies + sec * HZ;  in start_int_poll_timer()
241 	add_timer(&ctrl->poll_timer);  in start_int_poll_timer()
244 static inline int is_ctrl_busy(struct controller *ctrl)  in is_ctrl_busy()  argument
246 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);  in is_ctrl_busy()
254 static inline int shpc_poll_ctrl_busy(struct controller *ctrl)  in shpc_poll_ctrl_busy()  argument
258 	if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
264 		if (!is_ctrl_busy(ctrl))  in shpc_poll_ctrl_busy()
271 static inline int shpc_wait_cmd(struct controller *ctrl)  in shpc_wait_cmd()  argument
278 		rc = shpc_poll_ctrl_busy(ctrl);  in shpc_wait_cmd()
280 		rc = wait_event_interruptible_timeout(ctrl->queue,  in shpc_wait_cmd()
281 						!is_ctrl_busy(ctrl), timeout);  in shpc_wait_cmd()
282 	if (!rc && is_ctrl_busy(ctrl)) {  in shpc_wait_cmd()
284 		ctrl_err(ctrl, "Command not completed in 1000 msec\n");  in shpc_wait_cmd()
287 		ctrl_info(ctrl, "Command was interrupted by a signal\n");  in shpc_wait_cmd()
295 	struct controller *ctrl = slot->ctrl;  in shpc_write_cmd()  local
300 	mutex_lock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
302 	if (!shpc_poll_ctrl_busy(ctrl)) {  in shpc_write_cmd()
304 		ctrl_err(ctrl, "Controller is still busy after 1 sec\n");  in shpc_write_cmd()
311 	ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);  in shpc_write_cmd()
316 	shpc_writew(ctrl, CMD, temp_word);  in shpc_write_cmd()
321 	retval = shpc_wait_cmd(slot->ctrl);  in shpc_write_cmd()
325 	cmd_status = hpc_check_cmd_status(slot->ctrl);  in shpc_write_cmd()
327 		ctrl_err(ctrl, "Failed to issued command 0x%x (error code = %d)\n",  in shpc_write_cmd()
332 	mutex_unlock(&slot->ctrl->cmd_lock);  in shpc_write_cmd()
336 static int hpc_check_cmd_status(struct controller *ctrl)  in hpc_check_cmd_status()  argument
339 	u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;  in hpc_check_cmd_status()
347 		ctrl_err(ctrl, "Switch opened!\n");  in hpc_check_cmd_status()
351 		ctrl_err(ctrl, "Invalid HPC command!\n");  in hpc_check_cmd_status()
355 		ctrl_err(ctrl, "Invalid bus speed/mode!\n");  in hpc_check_cmd_status()
367 	struct controller *ctrl = slot->ctrl;  in hpc_get_attention_status()  local
368 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_attention_status()
391 	struct controller *ctrl = slot->ctrl;  in hpc_get_power_status()  local
392 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_power_status()
416 	struct controller *ctrl = slot->ctrl;  in hpc_get_latch_status()  local
417 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_latch_status()
426 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_status()  local
427 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_status()
437 	struct controller *ctrl = slot->ctrl;  in hpc_get_prog_int()  local
439 	*prog_int = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_prog_int()
447 	struct controller *ctrl = slot->ctrl;  in hpc_get_adapter_speed()  local
448 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_get_adapter_speed()
467 	ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",  in hpc_get_adapter_speed()
493 	ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);  in hpc_get_adapter_speed()
500 	struct controller *ctrl = slot->ctrl;  in hpc_get_mode1_ECC_cap()  local
501 	u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);  in hpc_get_mode1_ECC_cap()
502 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_get_mode1_ECC_cap()
510 	ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);  in hpc_get_mode1_ECC_cap()
516 	struct controller *ctrl = slot->ctrl;  in hpc_query_power_fault()  local
517 	u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));  in hpc_query_power_fault()
560 static void hpc_release_ctlr(struct controller *ctrl)  in hpc_release_ctlr()  argument
568 	for (i = 0; i < ctrl->num_slots; i++) {  in hpc_release_ctlr()
569 		slot_reg = shpc_readl(ctrl, SLOT_REG(i));  in hpc_release_ctlr()
575 		shpc_writel(ctrl, SLOT_REG(i), slot_reg);  in hpc_release_ctlr()
578 	cleanup_slots(ctrl);  in hpc_release_ctlr()
583 	serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in hpc_release_ctlr()
587 	shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in hpc_release_ctlr()
590 		del_timer(&ctrl->poll_timer);  in hpc_release_ctlr()
592 		free_irq(ctrl->pci_dev->irq, ctrl);  in hpc_release_ctlr()
593 		pci_disable_msi(ctrl->pci_dev);  in hpc_release_ctlr()
596 	iounmap(ctrl->creg);  in hpc_release_ctlr()
597 	release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in hpc_release_ctlr()
606 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_power_on_slot()
619 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_enable()
632 		ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);  in hpc_slot_disable()
637 static int shpc_get_cur_bus_speed(struct controller *ctrl)  in shpc_get_cur_bus_speed()  argument
640 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_cur_bus_speed()
642 	u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);  in shpc_get_cur_bus_speed()
643 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_cur_bus_speed()
709 	struct controller *ctrl = slot->ctrl;  in hpc_set_bus_speed_mode()  local
712 	pi = shpc_readb(ctrl, PROG_INTERFACE);  in hpc_set_bus_speed_mode()
765 		ctrl_err(ctrl, "%s: Write command failed!\n", __func__);  in hpc_set_bus_speed_mode()
767 		shpc_get_cur_bus_speed(ctrl);  in hpc_set_bus_speed_mode()
774 	struct controller *ctrl = (struct controller *)dev_id;  in shpc_isr()  local
779 	intr_loc = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
783 	ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);  in shpc_isr()
790 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
793 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
795 		intr_loc2 = shpc_readl(ctrl, INTR_LOC);  in shpc_isr()
796 		ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);  in shpc_isr()
805 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
807 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
809 		wake_up_interruptible(&ctrl->queue);  in shpc_isr()
815 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_isr()
820 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_isr()
821 		ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",  in shpc_isr()
825 			shpchp_handle_switch_change(hp_slot, ctrl);  in shpc_isr()
828 			shpchp_handle_attention_button(hp_slot, ctrl);  in shpc_isr()
831 			shpchp_handle_presence_change(hp_slot, ctrl);  in shpc_isr()
834 			shpchp_handle_power_fault(hp_slot, ctrl);  in shpc_isr()
838 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_isr()
843 		serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_isr()
845 		shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);  in shpc_isr()
851 static int shpc_get_max_bus_speed(struct controller *ctrl)  in shpc_get_max_bus_speed()  argument
854 	struct pci_bus *bus = ctrl->pci_dev->subordinate;  in shpc_get_max_bus_speed()
856 	u8 pi = shpc_readb(ctrl, PROG_INTERFACE);  in shpc_get_max_bus_speed()
857 	u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);  in shpc_get_max_bus_speed()
858 	u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);  in shpc_get_max_bus_speed()
891 	ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);  in shpc_get_max_bus_speed()
919 int shpc_init(struct controller *ctrl, struct pci_dev *pdev)  in shpc_init()  argument
927 	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */  in shpc_init()
928 	ctrl_dbg(ctrl, "Hotplug Controller:\n");  in shpc_init()
933 		ctrl->mmio_base = pci_resource_start(pdev, 0);  in shpc_init()
934 		ctrl->mmio_size = pci_resource_len(pdev, 0);  in shpc_init()
936 		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);  in shpc_init()
937 		if (!ctrl->cap_offset) {  in shpc_init()
938 			ctrl_err(ctrl, "Cannot find PCI capability\n");  in shpc_init()
941 		ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);  in shpc_init()
943 		rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);  in shpc_init()
945 			ctrl_err(ctrl, "Cannot read base_offset\n");  in shpc_init()
949 		rc = shpc_indirect_read(ctrl, 3, &tempdword);  in shpc_init()
951 			ctrl_err(ctrl, "Cannot read slot config\n");  in shpc_init()
955 		ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);  in shpc_init()
958 			rc = shpc_indirect_read(ctrl, i, &tempdword);  in shpc_init()
960 				ctrl_err(ctrl, "Cannot read creg (index = %d)\n",  in shpc_init()
964 			ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);  in shpc_init()
967 		ctrl->mmio_base =  in shpc_init()
969 		ctrl->mmio_size = 0x24 + 0x4 * num_slots;  in shpc_init()
972 	ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",  in shpc_init()
978 		ctrl_err(ctrl, "pci_enable_device failed\n");  in shpc_init()
982 	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {  in shpc_init()
983 		ctrl_err(ctrl, "Cannot reserve MMIO region\n");  in shpc_init()
988 	ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
989 	if (!ctrl->creg) {  in shpc_init()
990 		ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",  in shpc_init()
991 			 ctrl->mmio_size, ctrl->mmio_base);  in shpc_init()
992 		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);  in shpc_init()
996 	ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);  in shpc_init()
998 	mutex_init(&ctrl->crit_sect);  in shpc_init()
999 	mutex_init(&ctrl->cmd_lock);  in shpc_init()
1002 	init_waitqueue_head(&ctrl->queue);  in shpc_init()
1004 	ctrl->hpc_ops = &shpchp_hpc_ops;  in shpc_init()
1007 	slot_config = shpc_readl(ctrl, SLOT_CONFIG);  in shpc_init()
1008 	ctrl->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;  in shpc_init()
1009 	ctrl->num_slots = slot_config & SLOT_NUM;  in shpc_init()
1010 	ctrl->first_slot = (slot_config & PSN) >> 16;  in shpc_init()
1011 	ctrl->slot_num_inc = ((slot_config & UPDOWN) >> 29) ? 1 : -1;  in shpc_init()
1014 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1015 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1019 	shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1020 	tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1021 	ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1026 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1027 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1028 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1035 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1040 		timer_setup(&ctrl->poll_timer, int_poll_timeout, 0);  in shpc_init()
1041 		start_int_poll_timer(ctrl, 10);  in shpc_init()
1046 			ctrl_info(ctrl, "Can't get msi for the hotplug controller\n");  in shpc_init()
1047 			ctrl_info(ctrl, "Use INTx for the hotplug controller\n");  in shpc_init()
1052 		rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,  in shpc_init()
1053 				 MY_NAME, (void *)ctrl);  in shpc_init()
1054 		ctrl_dbg(ctrl, "request_irq %d (returns %d)\n",  in shpc_init()
1055 			 ctrl->pci_dev->irq, rc);  in shpc_init()
1057 			ctrl_err(ctrl, "Can't get irq %d for the hotplug controller\n",  in shpc_init()
1058 				 ctrl->pci_dev->irq);  in shpc_init()
1062 	ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);  in shpc_init()
1064 	shpc_get_max_bus_speed(ctrl);  in shpc_init()
1065 	shpc_get_cur_bus_speed(ctrl);  in shpc_init()
1070 	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {  in shpc_init()
1071 		slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));  in shpc_init()
1072 		ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",  in shpc_init()
1077 		shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);  in shpc_init()
1081 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1084 		shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);  in shpc_init()
1085 		tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);  in shpc_init()
1086 		ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);  in shpc_init()
1093 	iounmap(ctrl->creg);  in shpc_init()