17  * default behavior.
34  * Reads and Writes will be filtered by specified behavior. All other bits not
367 	const struct pci_bridge_reg_behavior *behavior;  in pci_bridge_emul_conf_read()  local
383 		behavior = bridge->pcie_cap_regs_behavior;  in pci_bridge_emul_conf_read()
387 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_read()
402 	*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |  in pci_bridge_emul_conf_read()
403 		  behavior[reg / 4].w1c;  in pci_bridge_emul_conf_read()
429 	const struct pci_bridge_reg_behavior *behavior;  in pci_bridge_emul_conf_write()  local
456 		behavior = bridge->pcie_cap_regs_behavior;  in pci_bridge_emul_conf_write()
460 		behavior = bridge->pci_regs_behavior;  in pci_bridge_emul_conf_write()
464 	new = old & (~mask | ~behavior[reg / 4].rw);  in pci_bridge_emul_conf_write()
467 	new |= (value << shift) & (behavior[reg / 4].rw & mask);  in pci_bridge_emul_conf_write()
470 	new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));  in pci_bridge_emul_conf_write()
479 	new &= ~(behavior[reg / 4].w1c & ~mask);  in pci_bridge_emul_conf_write()
485 	new |= (value << shift) & (behavior[reg / 4].w1c & mask);  in pci_bridge_emul_conf_write()