29 #define ASPM_STATE_L0S_UP	(1)	/* Upstream direction L0s state */
50 	struct pci_dev *pdev;		/* Upstream component of the Link */
70 	struct aspm_latency latency_up;	/* Upstream direction exit latency */
267 	/* Check upstream component if bit Slot Clock Configuration is 1 */  in pcie_aspm_configure_common_clock()
300 	/* Configure upstream component */  in pcie_aspm_configure_common_clock()
409 		/* Check upstream direction L0s latency */  in pcie_aspm_check_latency()
538 	/* Program Common_Mode_Restore_Time in upstream device */  in aspm_calc_l1ss_info()
587 	 * Re-read upstream/downstream components' register state after  in pcie_aspm_cap_init()
760 	u32 upstream = 0, dwstream = 0;  in pcie_config_aspm_link()  local
780 	/* Convert ASPM state to upstream/downstream ASPM register state */  in pcie_config_aspm_link()
784 		upstream |= PCI_EXP_LNKCTL_ASPM_L0S;  in pcie_config_aspm_link()
786 		upstream |= PCI_EXP_LNKCTL_ASPM_L1;  in pcie_config_aspm_link()
796 	 * upstream component first and then downstream, and vice  in pcie_config_aspm_link()
800 		pcie_config_aspm_dev(parent, upstream);  in pcie_config_aspm_link()
804 		pcie_config_aspm_dev(parent, upstream);  in pcie_config_aspm_link()
924 	 * We allocate pcie_link_state for the component on the upstream  in pcie_aspm_init_link_state()
946 	 * upstream links also because capable state of them can be  in pcie_aspm_init_link_state()
1021 	 * switch upstream port, this link state is parent_link to all  in pcie_aspm_exit_link_state()
1031 	/* Recheck latencies and configure upstream links */  in pcie_aspm_exit_link_state()
1207  * Relies on the upstream bridge's link_state being valid.  The link_state