Lines Matching +full:cci +full:- +full:400
1 // SPDX-License-Identifier: GPL-2.0
2 // CCI Cache Coherent Interconnect PMU driver
3 // Copyright (C) 2013-2018 Arm Ltd.
6 #include <linux/arm-cci.h>
19 #define DRIVER_NAME "ARM-CCI PMU"
38 #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size)
40 #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
41 #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1)
44 ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
80 * @fixed_hw_cntrs - Number of fixed event counters
81 * @num_hw_cntrs - Maximum number of programmable event counters
82 * @cntr_size - Size of an event counter mapping
165 * Instead of an event id to monitor CCI cycles, a dedicated counter is
166 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
177 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
217 CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
218 CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-7"),
309 return snprintf(buf, PAGE_SIZE, "config=0x%lx\n", (unsigned long)eattr->var); in cci400_pmu_cycle_event_show()
320 if (test_and_set_bit(CCI400_PMU_CYCLE_CNTR_IDX, hw->used_mask)) in cci400_get_event_idx()
321 return -EAGAIN; in cci400_get_event_idx()
327 if (!test_and_set_bit(idx, hw->used_mask)) in cci400_get_event_idx()
331 return -EAGAIN; in cci400_get_event_idx()
341 return -ENOENT; in cci400_validate_hw_event()
362 return -ENOENT; in cci400_validate_hw_event()
365 if (ev_code >= cci_pmu->model->event_ranges[if_type].min && in cci400_validate_hw_event()
366 ev_code <= cci_pmu->model->event_ranges[if_type].max) in cci400_validate_hw_event()
369 return -ENOENT; in cci400_validate_hw_event()
375 rev = readl_relaxed(cci_pmu->ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; in probe_cci400_revision()
400 * CCI5xx PMU event id is an 9-bit value made of two parts.
401 * bits [8:5] - Source for the event
402 * bits [4:0] - Event code (specific to type of interface)
453 CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
454 CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-8"),
529 (unsigned long)eattr->var, CCI5xx_PORT_GLOBAL); in cci5xx_pmu_global_event_show()
536 * 0x0-0x6 - Slave interfaces
537 * 0x8-0xD - Master interfaces
538 * 0xf - Global Events
539 * 0x7,0xe - Reserved
549 return -ENOENT; in cci500_validate_hw_event()
573 return -ENOENT; in cci500_validate_hw_event()
576 if (ev_code >= cci_pmu->model->event_ranges[if_type].min && in cci500_validate_hw_event()
577 ev_code <= cci_pmu->model->event_ranges[if_type].max) in cci500_validate_hw_event()
580 return -ENOENT; in cci500_validate_hw_event()
587 * 0x0-0x6 - Slave interfaces
588 * 0x8-0xe - Master interfaces
589 * 0xf - Global Events
590 * 0x7 - Reserved
600 return -ENOENT; in cci550_validate_hw_event()
625 return -ENOENT; in cci550_validate_hw_event()
628 if (ev_code >= cci_pmu->model->event_ranges[if_type].min && in cci550_validate_hw_event()
629 ev_code <= cci_pmu->model->event_ranges[if_type].max) in cci550_validate_hw_event()
632 return -ENOENT; in cci550_validate_hw_event()
638 * Program the CCI PMU counters which have PERF_HES_ARCH set
645 struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events; in cci_pmu_sync_counters()
648 bitmap_zero(mask, cci_pmu->num_cntrs); in cci_pmu_sync_counters()
649 for_each_set_bit(i, cci_pmu->hw_events.used_mask, cci_pmu->num_cntrs) { in cci_pmu_sync_counters()
650 struct perf_event *event = cci_hw->events[i]; in cci_pmu_sync_counters()
656 if (event->hw.state & PERF_HES_STOPPED) in cci_pmu_sync_counters()
658 if (event->hw.state & PERF_HES_ARCH) { in cci_pmu_sync_counters()
660 event->hw.state &= ~PERF_HES_ARCH; in cci_pmu_sync_counters()
667 /* Should be called with cci_pmu->hw_events->pmu_lock held */
673 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; in __cci_pmu_enable_nosync()
674 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_enable_nosync()
677 /* Should be called with cci_pmu->hw_events->pmu_lock held */
684 /* Should be called with cci_pmu->hw_events->pmu_lock held */
690 val = readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; in __cci_pmu_disable()
691 writel(val, cci_pmu->ctrl_base + CCI_PMCR); in __cci_pmu_disable()
699 return snprintf(buf, PAGE_SIZE, "%s\n", (char *)eattr->var); in cci_pmu_format_show()
709 (unsigned long)eattr->var); in cci_pmu_event_show()
719 return readl_relaxed(cci_pmu->base + in pmu_read_register()
720 CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); in pmu_read_register()
726 writel_relaxed(value, cci_pmu->base + in pmu_write_register()
727 CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); in pmu_write_register()
752 * For all counters on the CCI-PMU, disable any 'enabled' counters,
759 * cci_pm->hw_events->pmu_lock).
768 for (i = 0; i < cci_pmu->num_cntrs; i++) { in pmu_save_counters()
785 for_each_set_bit(i, mask, cci_pmu->num_cntrs) in pmu_restore_counters()
791 * by the cci
795 return (readl_relaxed(cci_pmu->ctrl_base + CCI_PMCR) & in pmu_get_max_counters()
801 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in pmu_get_event_idx()
802 unsigned long cci_event = event->hw.config_base; in pmu_get_event_idx()
805 if (cci_pmu->model->get_event_idx) in pmu_get_event_idx()
806 return cci_pmu->model->get_event_idx(cci_pmu, hw, cci_event); in pmu_get_event_idx()
810 if (!test_and_set_bit(idx, hw->used_mask)) in pmu_get_event_idx()
814 return -EAGAIN; in pmu_get_event_idx()
819 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in pmu_map_event()
821 if (event->attr.type < PERF_TYPE_MAX || in pmu_map_event()
822 !cci_pmu->model->validate_hw_event) in pmu_map_event()
823 return -ENOENT; in pmu_map_event()
825 return cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config); in pmu_map_event()
831 struct platform_device *pmu_device = cci_pmu->plat_device; in pmu_request_irq()
834 return -ENODEV; in pmu_request_irq()
836 if (cci_pmu->nr_irqs < 1) { in pmu_request_irq()
837 dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); in pmu_request_irq()
838 return -ENODEV; in pmu_request_irq()
842 * Register all available CCI PMU interrupts. In the interrupt handler in pmu_request_irq()
846 * This should allow handling of non-unique interrupt for the counters. in pmu_request_irq()
848 for (i = 0; i < cci_pmu->nr_irqs; i++) { in pmu_request_irq()
849 int err = request_irq(cci_pmu->irqs[i], handler, IRQF_SHARED, in pmu_request_irq()
850 "arm-cci-pmu", cci_pmu); in pmu_request_irq()
852 dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n", in pmu_request_irq()
853 cci_pmu->irqs[i]); in pmu_request_irq()
857 set_bit(i, &cci_pmu->active_irqs); in pmu_request_irq()
867 for (i = 0; i < cci_pmu->nr_irqs; i++) { in pmu_free_irq()
868 if (!test_and_clear_bit(i, &cci_pmu->active_irqs)) in pmu_free_irq()
871 free_irq(cci_pmu->irqs[i], cci_pmu); in pmu_free_irq()
877 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in pmu_read_counter()
878 struct hw_perf_event *hw_counter = &event->hw; in pmu_read_counter()
879 int idx = hw_counter->idx; in pmu_read_counter()
883 dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); in pmu_read_counter()
899 struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events; in __pmu_write_counters()
901 for_each_set_bit(i, mask, cci_pmu->num_cntrs) { in __pmu_write_counters()
902 struct perf_event *event = cci_hw->events[i]; in __pmu_write_counters()
906 pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i); in __pmu_write_counters()
912 if (cci_pmu->model->write_counters) in pmu_write_counters()
913 cci_pmu->model->write_counters(cci_pmu, mask); in pmu_write_counters()
921 * CCI-500/CCI-550 has advanced power saving policies, which could gate the
932 * For each counter to be programmed, repeat steps 3-7:
944 * We choose an event which for CCI-5xx is guaranteed not to count.
954 bitmap_zero(saved_mask, cci_pmu->num_cntrs); in cci5xx_pmu_write_counters()
963 for_each_set_bit(i, mask, cci_pmu->num_cntrs) { in cci5xx_pmu_write_counters()
964 struct perf_event *event = cci_pmu->hw_events.events[i]; in cci5xx_pmu_write_counters()
971 pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i); in cci5xx_pmu_write_counters()
973 pmu_set_event(cci_pmu, i, event->hw.config_base); in cci5xx_pmu_write_counters()
985 struct hw_perf_event *hwc = &event->hw; in pmu_event_update()
989 prev_raw_count = local64_read(&hwc->prev_count); in pmu_event_update()
991 } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, in pmu_event_update()
994 delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK; in pmu_event_update()
996 local64_add(delta, &event->count); in pmu_event_update()
1008 struct hw_perf_event *hwc = &event->hw; in pmu_event_set_period()
1010 * The CCI PMU counters have a period of 2^32. To account for the in pmu_event_set_period()
1016 local64_set(&hwc->prev_count, val); in pmu_event_set_period()
1019 * CCI PMU uses PERF_HES_ARCH to keep track of the counters, whose in pmu_event_set_period()
1020 * values needs to be sync-ed with the s/w state before the PMU is in pmu_event_set_period()
1024 hwc->state |= PERF_HES_ARCH; in pmu_event_set_period()
1031 struct cci_pmu_hw_events *events = &cci_pmu->hw_events; in pmu_handle_irq()
1034 raw_spin_lock_irqsave(&events->pmu_lock, flags); in pmu_handle_irq()
1040 * This should work regardless of whether we have per-counter overflow in pmu_handle_irq()
1044 struct perf_event *event = events->events[idx]; in pmu_handle_irq()
1064 raw_spin_unlock_irqrestore(&events->pmu_lock, flags); in pmu_handle_irq()
1086 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in hw_perf_event_destroy()
1087 atomic_t *active_events = &cci_pmu->active_events; in hw_perf_event_destroy()
1088 struct mutex *reserve_mutex = &cci_pmu->reserve_mutex; in hw_perf_event_destroy()
1099 struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; in cci_pmu_enable()
1100 int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs); in cci_pmu_enable()
1106 raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); in cci_pmu_enable()
1108 raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); in cci_pmu_enable()
1115 struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; in cci_pmu_disable()
1118 raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); in cci_pmu_disable()
1120 raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); in cci_pmu_disable()
1124 * Check if the idx represents a non-programmable counter.
1130 return (idx >= 0) && (idx < cci_pmu->model->fixed_hw_cntrs); in pmu_fixed_hw_idx()
1135 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in cci_pmu_start()
1136 struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; in cci_pmu_start()
1137 struct hw_perf_event *hwc = &event->hw; in cci_pmu_start()
1138 int idx = hwc->idx; in cci_pmu_start()
1146 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); in cci_pmu_start()
1148 hwc->state = 0; in cci_pmu_start()
1151 dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); in cci_pmu_start()
1155 raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); in cci_pmu_start()
1159 pmu_set_event(cci_pmu, idx, hwc->config_base); in cci_pmu_start()
1164 raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); in cci_pmu_start()
1169 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in cci_pmu_stop()
1170 struct hw_perf_event *hwc = &event->hw; in cci_pmu_stop()
1171 int idx = hwc->idx; in cci_pmu_stop()
1173 if (hwc->state & PERF_HES_STOPPED) in cci_pmu_stop()
1177 dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); in cci_pmu_stop()
1187 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; in cci_pmu_stop()
1192 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in cci_pmu_add()
1193 struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; in cci_pmu_add()
1194 struct hw_perf_event *hwc = &event->hw; in cci_pmu_add()
1202 event->hw.idx = idx; in cci_pmu_add()
1203 hw_events->events[idx] = event; in cci_pmu_add()
1205 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; in cci_pmu_add()
1217 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in cci_pmu_del()
1218 struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; in cci_pmu_del()
1219 struct hw_perf_event *hwc = &event->hw; in cci_pmu_del()
1220 int idx = hwc->idx; in cci_pmu_del()
1223 hw_events->events[idx] = NULL; in cci_pmu_del()
1224 clear_bit(idx, hw_events->used_mask); in cci_pmu_del()
1237 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The in validate_event()
1238 * core perf code won't check that the pmu->ctx == leader->ctx in validate_event()
1239 * until after pmu->event_init(event). in validate_event()
1241 if (event->pmu != cci_pmu) in validate_event()
1244 if (event->state < PERF_EVENT_STATE_OFF) in validate_event()
1247 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) in validate_event()
1255 struct perf_event *sibling, *leader = event->group_leader; in validate_group()
1256 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in validate_group()
1265 memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long)); in validate_group()
1267 if (!validate_event(event->pmu, &fake_pmu, leader)) in validate_group()
1268 return -EINVAL; in validate_group()
1271 if (!validate_event(event->pmu, &fake_pmu, sibling)) in validate_group()
1272 return -EINVAL; in validate_group()
1275 if (!validate_event(event->pmu, &fake_pmu, event)) in validate_group()
1276 return -EINVAL; in validate_group()
1283 struct hw_perf_event *hwc = &event->hw; in __hw_perf_event_init()
1289 pr_debug("event %x:%llx not supported\n", event->attr.type, in __hw_perf_event_init()
1290 event->attr.config); in __hw_perf_event_init()
1296 * hardware. Use -1 to signify that we haven't decided where to put it in __hw_perf_event_init()
1299 hwc->idx = -1; in __hw_perf_event_init()
1300 hwc->config_base = 0; in __hw_perf_event_init()
1301 hwc->config = 0; in __hw_perf_event_init()
1302 hwc->event_base = 0; in __hw_perf_event_init()
1307 hwc->config_base |= (unsigned long)mapping; in __hw_perf_event_init()
1309 if (event->group_leader != event) { in __hw_perf_event_init()
1311 return -EINVAL; in __hw_perf_event_init()
1319 struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); in cci_pmu_event_init()
1320 atomic_t *active_events = &cci_pmu->active_events; in cci_pmu_event_init()
1323 if (event->attr.type != event->pmu->type) in cci_pmu_event_init()
1324 return -ENOENT; in cci_pmu_event_init()
1327 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) in cci_pmu_event_init()
1328 return -EOPNOTSUPP; in cci_pmu_event_init()
1333 * handle cpu == -1 and pid == -1 for this case. in cci_pmu_event_init()
1339 if (event->cpu < 0) in cci_pmu_event_init()
1340 return -EINVAL; in cci_pmu_event_init()
1341 event->cpu = cci_pmu->cpu; in cci_pmu_event_init()
1343 event->destroy = hw_perf_event_destroy; in cci_pmu_event_init()
1345 mutex_lock(&cci_pmu->reserve_mutex); in cci_pmu_event_init()
1350 mutex_unlock(&cci_pmu->reserve_mutex); in cci_pmu_event_init()
1368 return cpumap_print_to_pagebuf(true, buf, cpumask_of(cci_pmu->cpu)); in pmu_cpumask_attr_show()
1402 const struct cci_pmu_model *model = cci_pmu->model; in cci_pmu_init()
1403 char *name = model->name; in cci_pmu_init()
1406 if (WARN_ON(model->num_hw_cntrs > NUM_HW_CNTRS_MAX)) in cci_pmu_init()
1407 return -EINVAL; in cci_pmu_init()
1408 if (WARN_ON(model->fixed_hw_cntrs > FIXED_HW_CNTRS_MAX)) in cci_pmu_init()
1409 return -EINVAL; in cci_pmu_init()
1411 pmu_event_attr_group.attrs = model->event_attrs; in cci_pmu_init()
1412 pmu_format_attr_group.attrs = model->format_attrs; in cci_pmu_init()
1414 cci_pmu->pmu = (struct pmu) { in cci_pmu_init()
1416 .name = cci_pmu->model->name, in cci_pmu_init()
1430 cci_pmu->plat_device = pdev; in cci_pmu_init()
1432 if (num_cntrs > cci_pmu->model->num_hw_cntrs) { in cci_pmu_init()
1433 dev_warn(&pdev->dev, in cci_pmu_init()
1436 num_cntrs, cci_pmu->model->num_hw_cntrs); in cci_pmu_init()
1437 num_cntrs = cci_pmu->model->num_hw_cntrs; in cci_pmu_init()
1439 cci_pmu->num_cntrs = num_cntrs + cci_pmu->model->fixed_hw_cntrs; in cci_pmu_init()
1441 return perf_pmu_register(&cci_pmu->pmu, name, -1); in cci_pmu_init()
1448 if (!g_cci_pmu || cpu != g_cci_pmu->cpu) in cci_pmu_offline_cpu()
1455 perf_pmu_migrate_context(&g_cci_pmu->pmu, cpu, target); in cci_pmu_offline_cpu()
1456 g_cci_pmu->cpu = target; in cci_pmu_offline_cpu()
1558 .compatible = "arm,cci-400-pmu",
1562 .compatible = "arm,cci-400-pmu,r0",
1566 .compatible = "arm,cci-400-pmu,r1",
1572 .compatible = "arm,cci-500-pmu,r0",
1576 .compatible = "arm,cci-550-pmu,r0",
1607 return ERR_PTR(-ENOMEM); in cci_pmu_alloc()
1609 cci_pmu->ctrl_base = *(void __iomem **)dev->platform_data; in cci_pmu_alloc()
1614 "DEPRECATED compatible property, requires secure access to CCI registers"); in cci_pmu_alloc()
1618 dev_warn(dev, "CCI PMU version not supported\n"); in cci_pmu_alloc()
1619 return ERR_PTR(-ENODEV); in cci_pmu_alloc()
1622 cci_pmu->model = model; in cci_pmu_alloc()
1623 cci_pmu->irqs = devm_kcalloc(dev, CCI_PMU_MAX_HW_CNTRS(model), in cci_pmu_alloc()
1624 sizeof(*cci_pmu->irqs), GFP_KERNEL); in cci_pmu_alloc()
1625 if (!cci_pmu->irqs) in cci_pmu_alloc()
1626 return ERR_PTR(-ENOMEM); in cci_pmu_alloc()
1627 cci_pmu->hw_events.events = devm_kcalloc(dev, in cci_pmu_alloc()
1629 sizeof(*cci_pmu->hw_events.events), in cci_pmu_alloc()
1631 if (!cci_pmu->hw_events.events) in cci_pmu_alloc()
1632 return ERR_PTR(-ENOMEM); in cci_pmu_alloc()
1633 cci_pmu->hw_events.used_mask = devm_kcalloc(dev, in cci_pmu_alloc()
1635 sizeof(*cci_pmu->hw_events.used_mask), in cci_pmu_alloc()
1637 if (!cci_pmu->hw_events.used_mask) in cci_pmu_alloc()
1638 return ERR_PTR(-ENOMEM); in cci_pmu_alloc()
1648 cci_pmu = cci_pmu_alloc(&pdev->dev); in cci_pmu_probe()
1652 cci_pmu->base = devm_platform_ioremap_resource(pdev, 0); in cci_pmu_probe()
1653 if (IS_ERR(cci_pmu->base)) in cci_pmu_probe()
1654 return -ENOMEM; in cci_pmu_probe()
1657 * CCI PMU has one overflow interrupt per counter; but some may be tied in cci_pmu_probe()
1660 cci_pmu->nr_irqs = 0; in cci_pmu_probe()
1661 for (i = 0; i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model); i++) { in cci_pmu_probe()
1666 if (is_duplicate_irq(irq, cci_pmu->irqs, cci_pmu->nr_irqs)) in cci_pmu_probe()
1669 cci_pmu->irqs[cci_pmu->nr_irqs++] = irq; in cci_pmu_probe()
1676 if (i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)) { in cci_pmu_probe()
1677 dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n", in cci_pmu_probe()
1678 i, CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)); in cci_pmu_probe()
1679 return -EINVAL; in cci_pmu_probe()
1682 raw_spin_lock_init(&cci_pmu->hw_events.pmu_lock); in cci_pmu_probe()
1683 mutex_init(&cci_pmu->reserve_mutex); in cci_pmu_probe()
1684 atomic_set(&cci_pmu->active_events, 0); in cci_pmu_probe()
1686 cci_pmu->cpu = raw_smp_processor_id(); in cci_pmu_probe()
1689 "perf/arm/cci:online", NULL, in cci_pmu_probe()
1696 pr_info("ARM %s PMU driver probed", cci_pmu->model->name); in cci_pmu_probe()
1711 perf_pmu_unregister(&g_cci_pmu->pmu); in cci_pmu_remove()
1729 MODULE_DESCRIPTION("ARM CCI PMU support");