Lines Matching full:fmreg
283 void __iomem *fmreg; member
327 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate() local
344 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
346 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
349 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
355 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
358 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
360 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
363 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, in hs_slew_rate_calibrate()
366 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); in hs_slew_rate_calibrate()
369 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
371 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); in hs_slew_rate_calibrate()
374 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
376 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1); in hs_slew_rate_calibrate()
799 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; in phy_v1_banks_init()
827 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; in phy_v2_banks_init()