Lines Matching +full:eye +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
19 /* version V1 sub-banks offset base address */
30 /* version V2 sub-banks offset base address */
213 /* CDR Charge Pump P-path current adjustment */
239 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
251 /* I-path capacitance adjustment for Gen1 */
326 struct u2phy_banks *u2_banks = &instance->u2_banks; in hs_slew_rate_calibrate()
327 void __iomem *fmreg = u2_banks->fmreg; in hs_slew_rate_calibrate()
328 void __iomem *com = u2_banks->com; in hs_slew_rate_calibrate()
334 if (instance->eye_src) in hs_slew_rate_calibrate()
352 if (tphy->pdata->version == MTK_PHY_V1) in hs_slew_rate_calibrate()
353 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1); in hs_slew_rate_calibrate()
380 tmp = tphy->src_ref_clk * tphy->src_coef; in hs_slew_rate_calibrate()
387 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in hs_slew_rate_calibrate()
388 instance->index, fm_out, calibration_val, in hs_slew_rate_calibrate()
389 tphy->src_ref_clk, tphy->src_coef); in hs_slew_rate_calibrate()
406 struct u3phy_banks *u3_banks = &instance->u3_banks; in u3_phy_instance_init()
410 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
412 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3); in u3_phy_instance_init()
415 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
418 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in u3_phy_instance_init()
420 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
423 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9); in u3_phy_instance_init()
425 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
428 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6); in u3_phy_instance_init()
430 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
433 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1); in u3_phy_instance_init()
435 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
438 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1); in u3_phy_instance_init()
440 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
443 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in u3_phy_instance_init()
445 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
448 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in u3_phy_instance_init()
450 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in u3_phy_instance_init()
456 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_init()
457 void __iomem *com = u2_banks->com; in u2_phy_instance_init()
458 u32 index = instance->index; in u2_phy_instance_init()
486 if (tphy->pdata->avoid_rx_sen_degradation) { in u2_phy_instance_init()
512 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_init()
518 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_power_on()
519 void __iomem *com = u2_banks->com; in u2_phy_instance_power_on()
520 u32 index = instance->index; in u2_phy_instance_power_on()
537 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_power_on()
546 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_power_on()
552 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_power_off()
553 void __iomem *com = u2_banks->com; in u2_phy_instance_power_off()
554 u32 index = instance->index; in u2_phy_instance_power_off()
571 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_power_off()
581 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); in u2_phy_instance_power_off()
587 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_exit()
588 void __iomem *com = u2_banks->com; in u2_phy_instance_exit()
589 u32 index = instance->index; in u2_phy_instance_exit()
592 if (tphy->pdata->avoid_rx_sen_degradation && index) { in u2_phy_instance_exit()
607 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_instance_set_mode()
610 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
625 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); in u2_phy_instance_set_mode()
631 struct u3phy_banks *u3_banks = &instance->u3_banks; in pcie_phy_instance_init()
634 if (tphy->pdata->version != MTK_PHY_V1) in pcie_phy_instance_init()
637 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
640 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0); in pcie_phy_instance_init()
643 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
646 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1); in pcie_phy_instance_init()
648 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
651 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0); in pcie_phy_instance_init()
653 /* SSC delta -5000ppm */ in pcie_phy_instance_init()
654 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
657 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20); in pcie_phy_instance_init()
659 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
662 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25); in pcie_phy_instance_init()
665 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
668 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5); in pcie_phy_instance_init()
670 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
673 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4); in pcie_phy_instance_init()
675 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
678 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6); in pcie_phy_instance_init()
680 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
683 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7); in pcie_phy_instance_init()
685 /* Tx Detect Rx Timing: 10us -> 5us */ in pcie_phy_instance_init()
686 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
689 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1); in pcie_phy_instance_init()
691 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
694 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2); in pcie_phy_instance_init()
698 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in pcie_phy_instance_init()
704 struct u3phy_banks *bank = &instance->u3_banks; in pcie_phy_instance_power_on()
707 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
709 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_on()
711 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
713 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_on()
720 struct u3phy_banks *bank = &instance->u3_banks; in pcie_phy_instance_power_off()
723 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
725 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD); in pcie_phy_instance_power_off()
727 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
729 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE); in pcie_phy_instance_power_off()
735 struct u3phy_banks *u3_banks = &instance->u3_banks; in sata_phy_instance_init()
736 void __iomem *phyd = u3_banks->phyd; in sata_phy_instance_init()
787 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); in sata_phy_instance_init()
793 struct u2phy_banks *u2_banks = &instance->u2_banks; in phy_v1_banks_init()
794 struct u3phy_banks *u3_banks = &instance->u3_banks; in phy_v1_banks_init()
796 switch (instance->type) { in phy_v1_banks_init()
798 u2_banks->misc = NULL; in phy_v1_banks_init()
799 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; in phy_v1_banks_init()
800 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; in phy_v1_banks_init()
804 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; in phy_v1_banks_init()
805 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; in phy_v1_banks_init()
806 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
807 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; in phy_v1_banks_init()
810 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; in phy_v1_banks_init()
813 dev_err(tphy->dev, "incompatible PHY type\n"); in phy_v1_banks_init()
821 struct u2phy_banks *u2_banks = &instance->u2_banks; in phy_v2_banks_init()
822 struct u3phy_banks *u3_banks = &instance->u3_banks; in phy_v2_banks_init()
824 switch (instance->type) { in phy_v2_banks_init()
826 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; in phy_v2_banks_init()
827 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; in phy_v2_banks_init()
828 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; in phy_v2_banks_init()
832 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; in phy_v2_banks_init()
833 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; in phy_v2_banks_init()
834 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; in phy_v2_banks_init()
835 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; in phy_v2_banks_init()
838 dev_err(tphy->dev, "incompatible PHY type\n"); in phy_v2_banks_init()
846 struct device *dev = &instance->phy->dev; in phy_parse_property()
848 if (instance->type != PHY_TYPE_USB2) in phy_parse_property()
851 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); in phy_parse_property()
852 device_property_read_u32(dev, "mediatek,eye-src", in phy_parse_property()
853 &instance->eye_src); in phy_parse_property()
854 device_property_read_u32(dev, "mediatek,eye-vrt", in phy_parse_property()
855 &instance->eye_vrt); in phy_parse_property()
856 device_property_read_u32(dev, "mediatek,eye-term", in phy_parse_property()
857 &instance->eye_term); in phy_parse_property()
859 &instance->intr); in phy_parse_property()
861 &instance->discth); in phy_parse_property()
862 dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", in phy_parse_property()
863 instance->bc12_en, instance->eye_src, in phy_parse_property()
864 instance->eye_vrt, instance->eye_term, in phy_parse_property()
865 instance->intr, instance->discth); in phy_parse_property()
871 struct u2phy_banks *u2_banks = &instance->u2_banks; in u2_phy_props_set()
872 void __iomem *com = u2_banks->com; in u2_phy_props_set()
875 if (instance->bc12_en) { in u2_phy_props_set()
881 if (instance->eye_src) { in u2_phy_props_set()
884 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src); in u2_phy_props_set()
888 if (instance->eye_vrt) { in u2_phy_props_set()
891 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt); in u2_phy_props_set()
895 if (instance->eye_term) { in u2_phy_props_set()
898 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term); in u2_phy_props_set()
902 if (instance->intr) { in u2_phy_props_set()
905 tmp |= PA1_RG_INTR_CAL_VAL(instance->intr); in u2_phy_props_set()
909 if (instance->discth) { in u2_phy_props_set()
912 tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth); in u2_phy_props_set()
920 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_init()
923 ret = clk_prepare_enable(instance->ref_clk); in mtk_phy_init()
925 dev_err(tphy->dev, "failed to enable ref_clk\n"); in mtk_phy_init()
929 ret = clk_prepare_enable(instance->da_ref_clk); in mtk_phy_init()
931 dev_err(tphy->dev, "failed to enable da_ref\n"); in mtk_phy_init()
932 clk_disable_unprepare(instance->ref_clk); in mtk_phy_init()
936 switch (instance->type) { in mtk_phy_init()
951 dev_err(tphy->dev, "incompatible PHY type\n"); in mtk_phy_init()
952 clk_disable_unprepare(instance->ref_clk); in mtk_phy_init()
953 clk_disable_unprepare(instance->da_ref_clk); in mtk_phy_init()
954 return -EINVAL; in mtk_phy_init()
963 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_power_on()
965 if (instance->type == PHY_TYPE_USB2) { in mtk_phy_power_on()
968 } else if (instance->type == PHY_TYPE_PCIE) { in mtk_phy_power_on()
978 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_power_off()
980 if (instance->type == PHY_TYPE_USB2) in mtk_phy_power_off()
982 else if (instance->type == PHY_TYPE_PCIE) in mtk_phy_power_off()
991 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_exit()
993 if (instance->type == PHY_TYPE_USB2) in mtk_phy_exit()
996 clk_disable_unprepare(instance->ref_clk); in mtk_phy_exit()
997 clk_disable_unprepare(instance->da_ref_clk); in mtk_phy_exit()
1004 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); in mtk_phy_set_mode()
1006 if (instance->type == PHY_TYPE_USB2) in mtk_phy_set_mode()
1017 struct device_node *phy_np = args->np; in mtk_phy_xlate()
1020 if (args->args_count != 1) { in mtk_phy_xlate()
1022 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1025 for (index = 0; index < tphy->nphys; index++) in mtk_phy_xlate()
1026 if (phy_np == tphy->phys[index]->phy->dev.of_node) { in mtk_phy_xlate()
1027 instance = tphy->phys[index]; in mtk_phy_xlate()
1033 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1036 instance->type = args->args[0]; in mtk_phy_xlate()
1037 if (!(instance->type == PHY_TYPE_USB2 || in mtk_phy_xlate()
1038 instance->type == PHY_TYPE_USB3 || in mtk_phy_xlate()
1039 instance->type == PHY_TYPE_PCIE || in mtk_phy_xlate()
1040 instance->type == PHY_TYPE_SATA)) { in mtk_phy_xlate()
1041 dev_err(dev, "unsupported device type: %d\n", instance->type); in mtk_phy_xlate()
1042 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1045 if (tphy->pdata->version == MTK_PHY_V1) { in mtk_phy_xlate()
1047 } else if (tphy->pdata->version == MTK_PHY_V2) { in mtk_phy_xlate()
1051 return ERR_PTR(-EINVAL); in mtk_phy_xlate()
1056 return instance->phy; in mtk_phy_xlate()
1084 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata },
1085 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata },
1086 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata },
1087 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata },
1088 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata },
1095 struct device *dev = &pdev->dev; in mtk_tphy_probe()
1096 struct device_node *np = dev->of_node; in mtk_tphy_probe()
1106 return -ENOMEM; in mtk_tphy_probe()
1108 tphy->pdata = of_device_get_match_data(dev); in mtk_tphy_probe()
1109 if (!tphy->pdata) in mtk_tphy_probe()
1110 return -EINVAL; in mtk_tphy_probe()
1112 tphy->nphys = of_get_child_count(np); in mtk_tphy_probe()
1113 tphy->phys = devm_kcalloc(dev, tphy->nphys, in mtk_tphy_probe()
1114 sizeof(*tphy->phys), GFP_KERNEL); in mtk_tphy_probe()
1115 if (!tphy->phys) in mtk_tphy_probe()
1116 return -ENOMEM; in mtk_tphy_probe()
1118 tphy->dev = dev; in mtk_tphy_probe()
1123 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { in mtk_tphy_probe()
1125 tphy->sif_base = devm_ioremap_resource(dev, sif_res); in mtk_tphy_probe()
1126 if (IS_ERR(tphy->sif_base)) { in mtk_tphy_probe()
1128 return PTR_ERR(tphy->sif_base); in mtk_tphy_probe()
1132 tphy->src_ref_clk = U3P_REF_CLK; in mtk_tphy_probe()
1133 tphy->src_coef = U3P_SLEW_RATE_COEF; in mtk_tphy_probe()
1135 device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", in mtk_tphy_probe()
1136 &tphy->src_ref_clk); in mtk_tphy_probe()
1137 device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); in mtk_tphy_probe()
1146 retval = -ENOMEM; in mtk_tphy_probe()
1150 tphy->phys[port] = instance; in mtk_tphy_probe()
1161 dev_err(dev, "failed to get address resource(id-%d)\n", in mtk_tphy_probe()
1166 instance->port_base = devm_ioremap_resource(&phy->dev, &res); in mtk_tphy_probe()
1167 if (IS_ERR(instance->port_base)) { in mtk_tphy_probe()
1169 retval = PTR_ERR(instance->port_base); in mtk_tphy_probe()
1173 instance->phy = phy; in mtk_tphy_probe()
1174 instance->index = port; in mtk_tphy_probe()
1178 instance->ref_clk = devm_clk_get_optional(&phy->dev, "ref"); in mtk_tphy_probe()
1179 if (IS_ERR(instance->ref_clk)) { in mtk_tphy_probe()
1180 dev_err(dev, "failed to get ref_clk(id-%d)\n", port); in mtk_tphy_probe()
1181 retval = PTR_ERR(instance->ref_clk); in mtk_tphy_probe()
1185 instance->da_ref_clk = in mtk_tphy_probe()
1186 devm_clk_get_optional(&phy->dev, "da_ref"); in mtk_tphy_probe()
1187 if (IS_ERR(instance->da_ref_clk)) { in mtk_tphy_probe()
1188 dev_err(dev, "failed to get da_ref_clk(id-%d)\n", port); in mtk_tphy_probe()
1189 retval = PTR_ERR(instance->da_ref_clk); in mtk_tphy_probe()
1205 .name = "mtk-tphy",
1213 MODULE_DESCRIPTION("MediaTek T-PHY driver");