Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/nvmem-consumer.h>
16 #include <linux/phy/phy.h>
23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
105 * if yes, then offset gives index in the reg-layout
123 /* set of registers with offsets different per-PHY */
240 /* true if PHY has PLL_TEST register to select clk_scheme */
246 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
287 "vdda-pll", "vdda-phy-dpdm",
292 /* struct override_param - structure holding qusb2 v2 phy overriding param
301 /*struct override_params - structure holding qusb2 v2 phy overriding params
304 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register
305 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
321 * struct qusb2_phy - structure holding qusb2 phy attributes
323 * @phy: generic phy
324 * @base: iomapped memory space for qubs2 phy
327 * @ref_clk: phy reference clock
328 * @iface_clk: phy interface clock
329 * @phy_reset: phy reset control
333 * @cell: nvmem cell containing phy tuning value
337 * @cfg: phy config data
338 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
339 * @phy_initialized: indicate if PHY has been initialized
340 * @mode: current PHY mode
343 struct phy *phy; member
417 * Update board specific PHY tuning override values if specified from
422 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_override_phy_params()
423 struct override_params *or = &qphy->overrides; in qusb2_phy_override_phy_params()
425 if (or->imp_res_offset.override) in qusb2_phy_override_phy_params()
426 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, in qusb2_phy_override_phy_params()
427 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
430 if (or->bias_ctrl.override) in qusb2_phy_override_phy_params()
431 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, in qusb2_phy_override_phy_params()
432 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
435 if (or->charge_ctrl.override) in qusb2_phy_override_phy_params()
436 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, in qusb2_phy_override_phy_params()
437 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, in qusb2_phy_override_phy_params()
440 if (or->hstx_trim.override) in qusb2_phy_override_phy_params()
441 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
442 or->hstx_trim.value << HSTX_TRIM_SHIFT, in qusb2_phy_override_phy_params()
445 if (or->preemphasis.override) in qusb2_phy_override_phy_params()
446 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
447 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, in qusb2_phy_override_phy_params()
450 if (or->preemphasis_width.override) { in qusb2_phy_override_phy_params()
451 if (or->preemphasis_width.value == in qusb2_phy_override_phy_params()
453 qusb2_setbits(qphy->base, in qusb2_phy_override_phy_params()
454 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
457 qusb2_clrbits(qphy->base, in qusb2_phy_override_phy_params()
458 cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_override_phy_params()
462 if (or->hsdisc_trim.override) in qusb2_phy_override_phy_params()
463 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_override_phy_params()
464 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, in qusb2_phy_override_phy_params()
475 struct device *dev = &qphy->phy->dev; in qusb2_phy_set_tune2_param()
476 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_set_tune2_param()
480 if (!qphy->cell) in qusb2_phy_set_tune2_param()
488 * set while configuring the phy. in qusb2_phy_set_tune2_param()
490 val = nvmem_cell_read(qphy->cell, NULL); in qusb2_phy_set_tune2_param()
492 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
498 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); in qusb2_phy_set_tune2_param()
503 if (cfg->update_tune1_with_efuse) in qusb2_phy_set_tune2_param()
504 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], in qusb2_phy_set_tune2_param()
507 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], in qusb2_phy_set_tune2_param()
511 static int qusb2_phy_set_mode(struct phy *phy, in qusb2_phy_set_mode() argument
514 struct qusb2_phy *qphy = phy_get_drvdata(phy); in qusb2_phy_set_mode()
516 qphy->mode = mode; in qusb2_phy_set_mode()
524 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_suspend()
527 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_suspend()
529 if (!qphy->phy_initialized) { in qusb2_phy_runtime_suspend()
530 dev_vdbg(dev, "PHY not initialized, bailing out\n"); in qusb2_phy_runtime_suspend()
537 * current D+/D- levels are e.g. if currently D+ high, D- low in qusb2_phy_runtime_suspend()
538 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high in qusb2_phy_runtime_suspend()
541 switch (qphy->mode) { in qusb2_phy_runtime_suspend()
559 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_suspend()
562 if (cfg->has_pll_override) { in qusb2_phy_runtime_suspend()
563 qusb2_setbits(qphy->base, in qusb2_phy_runtime_suspend()
564 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_suspend()
569 /* enable phy auto-resume only if device is connected on bus */ in qusb2_phy_runtime_suspend()
570 if (qphy->mode != PHY_MODE_INVALID) { in qusb2_phy_runtime_suspend()
571 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
572 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
574 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], in qusb2_phy_runtime_suspend()
575 cfg->autoresume_en); in qusb2_phy_runtime_suspend()
578 if (!qphy->has_se_clk_scheme) in qusb2_phy_runtime_suspend()
579 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_runtime_suspend()
581 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_suspend()
582 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_suspend()
590 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_runtime_resume()
593 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); in qusb2_phy_runtime_resume()
595 if (!qphy->phy_initialized) { in qusb2_phy_runtime_resume()
596 dev_vdbg(dev, "PHY not initialized, bailing out\n"); in qusb2_phy_runtime_resume()
600 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_runtime_resume()
606 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
612 if (!qphy->has_se_clk_scheme) { in qusb2_phy_runtime_resume()
613 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_runtime_resume()
620 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); in qusb2_phy_runtime_resume()
623 if (cfg->has_pll_override) { in qusb2_phy_runtime_resume()
624 qusb2_clrbits(qphy->base, in qusb2_phy_runtime_resume()
625 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], in qusb2_phy_runtime_resume()
632 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_runtime_resume()
634 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_runtime_resume()
639 static int qusb2_phy_init(struct phy *phy) in qusb2_phy_init() argument
641 struct qusb2_phy *qphy = phy_get_drvdata(phy); in qusb2_phy_init()
642 const struct qusb2_phy_cfg *cfg = qphy->cfg; in qusb2_phy_init()
647 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); in qusb2_phy_init()
650 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
654 ret = clk_prepare_enable(qphy->iface_clk); in qusb2_phy_init()
656 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); in qusb2_phy_init()
660 /* enable ahb interface clock to program phy */ in qusb2_phy_init()
661 ret = clk_prepare_enable(qphy->cfg_ahb_clk); in qusb2_phy_init()
663 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); in qusb2_phy_init()
667 /* Perform phy reset */ in qusb2_phy_init()
668 ret = reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
670 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); in qusb2_phy_init()
674 /* 100 us delay to keep PHY in reset mode */ in qusb2_phy_init()
677 ret = reset_control_deassert(qphy->phy_reset); in qusb2_phy_init()
679 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); in qusb2_phy_init()
683 /* Disable the PHY */ in qusb2_phy_init()
684 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
685 qphy->cfg->disable_ctrl); in qusb2_phy_init()
687 if (cfg->has_pll_test) { in qusb2_phy_init()
689 val = readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
692 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, in qusb2_phy_init()
693 cfg->tbl_num); in qusb2_phy_init()
695 /* Override board specific PHY tuning values */ in qusb2_phy_init()
698 /* Set efuse value for tuning the PHY */ in qusb2_phy_init()
701 /* Enable the PHY */ in qusb2_phy_init()
702 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_init()
705 /* Required to get phy pll lock successfully */ in qusb2_phy_init()
708 /* Default is single-ended clock on msm8996 */ in qusb2_phy_init()
709 qphy->has_se_clk_scheme = true; in qusb2_phy_init()
711 * read TCSR_PHY_CLK_SCHEME register to check if single-ended in qusb2_phy_init()
713 * ref_clk and use single-ended clock, otherwise use differential in qusb2_phy_init()
716 if (qphy->tcsr) { in qusb2_phy_init()
717 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, in qusb2_phy_init()
720 dev_err(&phy->dev, "failed to read clk scheme reg\n"); in qusb2_phy_init()
726 dev_vdbg(&phy->dev, "%s(): select differential clk\n", in qusb2_phy_init()
728 qphy->has_se_clk_scheme = false; in qusb2_phy_init()
730 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", in qusb2_phy_init()
735 if (!qphy->has_se_clk_scheme) { in qusb2_phy_init()
736 ret = clk_prepare_enable(qphy->ref_clk); in qusb2_phy_init()
738 dev_err(&phy->dev, "failed to enable ref clk, %d\n", in qusb2_phy_init()
744 if (cfg->has_pll_test) { in qusb2_phy_init()
745 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
750 writel(val, qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
753 readl(qphy->base + QUSB2PHY_PLL_TEST); in qusb2_phy_init()
756 /* Required to get phy pll lock successfully */ in qusb2_phy_init()
759 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); in qusb2_phy_init()
760 if (!(val & cfg->mask_core_ready)) { in qusb2_phy_init()
761 dev_err(&phy->dev, in qusb2_phy_init()
763 ret = -EBUSY; in qusb2_phy_init()
766 qphy->phy_initialized = true; in qusb2_phy_init()
771 if (!qphy->has_se_clk_scheme) in qusb2_phy_init()
772 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_init()
774 reset_control_assert(qphy->phy_reset); in qusb2_phy_init()
776 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_init()
778 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_init()
780 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_init()
785 static int qusb2_phy_exit(struct phy *phy) in qusb2_phy_exit() argument
787 struct qusb2_phy *qphy = phy_get_drvdata(phy); in qusb2_phy_exit()
789 /* Disable the PHY */ in qusb2_phy_exit()
790 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], in qusb2_phy_exit()
791 qphy->cfg->disable_ctrl); in qusb2_phy_exit()
793 if (!qphy->has_se_clk_scheme) in qusb2_phy_exit()
794 clk_disable_unprepare(qphy->ref_clk); in qusb2_phy_exit()
796 reset_control_assert(qphy->phy_reset); in qusb2_phy_exit()
798 clk_disable_unprepare(qphy->cfg_ahb_clk); in qusb2_phy_exit()
799 clk_disable_unprepare(qphy->iface_clk); in qusb2_phy_exit()
801 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); in qusb2_phy_exit()
803 qphy->phy_initialized = false; in qusb2_phy_exit()
817 .compatible = "qcom,ipq8074-qusb2-phy",
820 .compatible = "qcom,msm8996-qusb2-phy",
823 .compatible = "qcom,msm8998-qusb2-phy",
828 * trees that didn't include "qcom,qusb2-v2-phy"
830 .compatible = "qcom,sdm845-qusb2-phy",
833 .compatible = "qcom,qusb2-v2-phy",
847 struct device *dev = &pdev->dev; in qusb2_phy_probe()
850 struct phy *generic_phy; in qusb2_phy_probe()
859 return -ENOMEM; in qusb2_phy_probe()
860 or = &qphy->overrides; in qusb2_phy_probe()
863 qphy->base = devm_ioremap_resource(dev, res); in qusb2_phy_probe()
864 if (IS_ERR(qphy->base)) in qusb2_phy_probe()
865 return PTR_ERR(qphy->base); in qusb2_phy_probe()
867 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); in qusb2_phy_probe()
868 if (IS_ERR(qphy->cfg_ahb_clk)) { in qusb2_phy_probe()
869 ret = PTR_ERR(qphy->cfg_ahb_clk); in qusb2_phy_probe()
870 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
875 qphy->ref_clk = devm_clk_get(dev, "ref"); in qusb2_phy_probe()
876 if (IS_ERR(qphy->ref_clk)) { in qusb2_phy_probe()
877 ret = PTR_ERR(qphy->ref_clk); in qusb2_phy_probe()
878 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
883 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); in qusb2_phy_probe()
884 if (IS_ERR(qphy->iface_clk)) in qusb2_phy_probe()
885 return PTR_ERR(qphy->iface_clk); in qusb2_phy_probe()
887 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); in qusb2_phy_probe()
888 if (IS_ERR(qphy->phy_reset)) { in qusb2_phy_probe()
889 dev_err(dev, "failed to get phy core reset\n"); in qusb2_phy_probe()
890 return PTR_ERR(qphy->phy_reset); in qusb2_phy_probe()
893 num = ARRAY_SIZE(qphy->vregs); in qusb2_phy_probe()
895 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; in qusb2_phy_probe()
897 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); in qusb2_phy_probe()
899 if (ret != -EPROBE_DEFER) in qusb2_phy_probe()
905 /* Get the specific init parameters of QMP phy */ in qusb2_phy_probe()
906 qphy->cfg = of_device_get_match_data(dev); in qusb2_phy_probe()
908 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, in qusb2_phy_probe()
909 "qcom,tcsr-syscon"); in qusb2_phy_probe()
910 if (IS_ERR(qphy->tcsr)) { in qusb2_phy_probe()
912 qphy->tcsr = NULL; in qusb2_phy_probe()
915 qphy->cell = devm_nvmem_cell_get(dev, NULL); in qusb2_phy_probe()
916 if (IS_ERR(qphy->cell)) { in qusb2_phy_probe()
917 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) in qusb2_phy_probe()
918 return -EPROBE_DEFER; in qusb2_phy_probe()
919 qphy->cell = NULL; in qusb2_phy_probe()
923 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", in qusb2_phy_probe()
925 or->imp_res_offset.value = (u8)value; in qusb2_phy_probe()
926 or->imp_res_offset.override = true; in qusb2_phy_probe()
929 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", in qusb2_phy_probe()
931 or->bias_ctrl.value = (u8)value; in qusb2_phy_probe()
932 or->bias_ctrl.override = true; in qusb2_phy_probe()
935 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", in qusb2_phy_probe()
937 or->charge_ctrl.value = (u8)value; in qusb2_phy_probe()
938 or->charge_ctrl.override = true; in qusb2_phy_probe()
941 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", in qusb2_phy_probe()
943 or->hstx_trim.value = (u8)value; in qusb2_phy_probe()
944 or->hstx_trim.override = true; in qusb2_phy_probe()
947 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", in qusb2_phy_probe()
949 or->preemphasis.value = (u8)value; in qusb2_phy_probe()
950 or->preemphasis.override = true; in qusb2_phy_probe()
953 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", in qusb2_phy_probe()
955 or->preemphasis_width.value = (u8)value; in qusb2_phy_probe()
956 or->preemphasis_width.override = true; in qusb2_phy_probe()
959 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", in qusb2_phy_probe()
961 or->hsdisc_trim.value = (u8)value; in qusb2_phy_probe()
962 or->hsdisc_trim.override = true; in qusb2_phy_probe()
976 dev_err(dev, "failed to create phy, %d\n", ret); in qusb2_phy_probe()
980 qphy->phy = generic_phy; in qusb2_phy_probe()
987 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); in qusb2_phy_probe()
997 .name = "qcom-qusb2-phy",
1006 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");