Lines Matching +full:xusb +full:- +full:padctl
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
18 #include "xusb.h"
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
31 /* XUSB PADCTL registers */
144 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl) in to_tegra186_xusb_padctl() argument
146 return container_of(padctl, struct tegra186_xusb_padctl, base); in to_tegra186_xusb_padctl()
159 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
161 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
162 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
163 usb2->base.index = index; in tegra186_usb2_lane_probe()
164 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
165 usb2->base.np = np; in tegra186_usb2_lane_probe()
167 err = tegra_xusb_lane_parse_dt(&usb2->base, np); in tegra186_usb2_lane_probe()
173 return &usb2->base; in tegra186_usb2_lane_probe()
188 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl) in tegra186_utmi_bias_pad_power_on() argument
190 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); in tegra186_utmi_bias_pad_power_on()
191 struct device *dev = padctl->dev; in tegra186_utmi_bias_pad_power_on()
195 mutex_lock(&padctl->lock); in tegra186_utmi_bias_pad_power_on()
197 if (priv->bias_pad_enable++ > 0) { in tegra186_utmi_bias_pad_power_on()
198 mutex_unlock(&padctl->lock); in tegra186_utmi_bias_pad_power_on()
202 err = clk_prepare_enable(priv->usb2_trk_clk); in tegra186_utmi_bias_pad_power_on()
206 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_on()
211 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_on()
213 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra186_utmi_bias_pad_power_on()
216 value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch); in tegra186_utmi_bias_pad_power_on()
217 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0); in tegra186_utmi_bias_pad_power_on()
221 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_on()
223 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_on()
225 mutex_unlock(&padctl->lock); in tegra186_utmi_bias_pad_power_on()
228 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl) in tegra186_utmi_bias_pad_power_off() argument
230 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); in tegra186_utmi_bias_pad_power_off()
233 mutex_lock(&padctl->lock); in tegra186_utmi_bias_pad_power_off()
235 if (WARN_ON(priv->bias_pad_enable == 0)) { in tegra186_utmi_bias_pad_power_off()
236 mutex_unlock(&padctl->lock); in tegra186_utmi_bias_pad_power_off()
240 if (--priv->bias_pad_enable > 0) { in tegra186_utmi_bias_pad_power_off()
241 mutex_unlock(&padctl->lock); in tegra186_utmi_bias_pad_power_off()
245 value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_off()
247 padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1); in tegra186_utmi_bias_pad_power_off()
249 clk_disable_unprepare(priv->usb2_trk_clk); in tegra186_utmi_bias_pad_power_off()
251 mutex_unlock(&padctl->lock); in tegra186_utmi_bias_pad_power_off()
257 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra_phy_xusb_utmi_pad_power_on() local
259 struct device *dev = padctl->dev; in tegra_phy_xusb_utmi_pad_power_on()
260 unsigned int index = lane->index; in tegra_phy_xusb_utmi_pad_power_on()
266 port = tegra_xusb_find_usb2_port(padctl, index); in tegra_phy_xusb_utmi_pad_power_on()
272 tegra186_utmi_bias_pad_power_on(padctl); in tegra_phy_xusb_utmi_pad_power_on()
276 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra_phy_xusb_utmi_pad_power_on()
278 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra_phy_xusb_utmi_pad_power_on()
280 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra_phy_xusb_utmi_pad_power_on()
282 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra_phy_xusb_utmi_pad_power_on()
288 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra_phy_xusb_utmi_pad_power_down() local
289 unsigned int index = lane->index; in tegra_phy_xusb_utmi_pad_power_down()
295 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra_phy_xusb_utmi_pad_power_down()
297 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra_phy_xusb_utmi_pad_power_down()
299 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra_phy_xusb_utmi_pad_power_down()
301 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra_phy_xusb_utmi_pad_power_down()
305 tegra186_utmi_bias_pad_power_off(padctl); in tegra_phy_xusb_utmi_pad_power_down()
308 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl, in tegra186_xusb_padctl_vbus_override() argument
313 dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear"); in tegra186_xusb_padctl_vbus_override()
315 value = padctl_readl(padctl, USB2_VBUS_ID); in tegra186_xusb_padctl_vbus_override()
325 padctl_writel(padctl, value, USB2_VBUS_ID); in tegra186_xusb_padctl_vbus_override()
330 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl, in tegra186_xusb_padctl_id_override() argument
335 dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear"); in tegra186_xusb_padctl_id_override()
337 value = padctl_readl(padctl, USB2_VBUS_ID); in tegra186_xusb_padctl_id_override()
342 padctl_writel(padctl, value, USB2_VBUS_ID); in tegra186_xusb_padctl_id_override()
345 value = padctl_readl(padctl, USB2_VBUS_ID); in tegra186_xusb_padctl_id_override()
355 padctl_writel(padctl, value, USB2_VBUS_ID); in tegra186_xusb_padctl_id_override()
364 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_phy_set_mode() local
365 struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl, in tegra186_utmi_phy_set_mode()
366 lane->index); in tegra186_utmi_phy_set_mode()
369 mutex_lock(&padctl->lock); in tegra186_utmi_phy_set_mode()
371 dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode); in tegra186_utmi_phy_set_mode()
375 tegra186_xusb_padctl_id_override(padctl, true); in tegra186_utmi_phy_set_mode()
377 err = regulator_enable(port->supply); in tegra186_utmi_phy_set_mode()
379 tegra186_xusb_padctl_vbus_override(padctl, true); in tegra186_utmi_phy_set_mode()
386 if (regulator_is_enabled(port->supply)) in tegra186_utmi_phy_set_mode()
387 regulator_disable(port->supply); in tegra186_utmi_phy_set_mode()
389 tegra186_xusb_padctl_id_override(padctl, false); in tegra186_utmi_phy_set_mode()
390 tegra186_xusb_padctl_vbus_override(padctl, false); in tegra186_utmi_phy_set_mode()
394 mutex_unlock(&padctl->lock); in tegra186_utmi_phy_set_mode()
403 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_phy_power_on() local
404 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); in tegra186_utmi_phy_power_on()
406 unsigned int index = lane->index; in tegra186_utmi_phy_power_on()
407 struct device *dev = padctl->dev; in tegra186_utmi_phy_power_on()
410 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_power_on()
413 return -ENODEV; in tegra186_utmi_phy_power_on()
416 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX); in tegra186_utmi_phy_power_on()
419 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX); in tegra186_utmi_phy_power_on()
421 value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP); in tegra186_utmi_phy_power_on()
424 if (port->mode == USB_DR_MODE_UNKNOWN) in tegra186_utmi_phy_power_on()
426 else if (port->mode == USB_DR_MODE_PERIPHERAL) in tegra186_utmi_phy_power_on()
428 else if (port->mode == USB_DR_MODE_HOST) in tegra186_utmi_phy_power_on()
430 else if (port->mode == USB_DR_MODE_OTG) in tegra186_utmi_phy_power_on()
433 padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP); in tegra186_utmi_phy_power_on()
435 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_phy_power_on()
440 if (usb2->hs_curr_level_offset) { in tegra186_utmi_phy_power_on()
443 hs_current_level = (int)priv->calib.hs_curr_level[index] + in tegra186_utmi_phy_power_on()
444 usb2->hs_curr_level_offset; in tegra186_utmi_phy_power_on()
453 value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]); in tegra186_utmi_phy_power_on()
456 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index)); in tegra186_utmi_phy_power_on()
458 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_phy_power_on()
460 value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj); in tegra186_utmi_phy_power_on()
462 value |= RPD_CTRL(priv->calib.rpd_ctrl); in tegra186_utmi_phy_power_on()
463 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index)); in tegra186_utmi_phy_power_on()
481 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_phy_init() local
483 unsigned int index = lane->index; in tegra186_utmi_phy_init()
484 struct device *dev = padctl->dev; in tegra186_utmi_phy_init()
487 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_init()
490 return -ENODEV; in tegra186_utmi_phy_init()
493 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra186_utmi_phy_init()
494 err = regulator_enable(port->supply); in tegra186_utmi_phy_init()
508 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_utmi_phy_exit() local
510 unsigned int index = lane->index; in tegra186_utmi_phy_exit()
511 struct device *dev = padctl->dev; in tegra186_utmi_phy_exit()
514 port = tegra_xusb_find_usb2_port(padctl, index); in tegra186_utmi_phy_exit()
517 return -ENODEV; in tegra186_utmi_phy_exit()
520 if (port->supply && port->mode == USB_DR_MODE_HOST) { in tegra186_utmi_phy_exit()
521 err = regulator_disable(port->supply); in tegra186_utmi_phy_exit()
542 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl, in tegra186_usb2_pad_probe() argument
546 struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl); in tegra186_usb2_pad_probe()
553 return ERR_PTR(-ENOMEM); in tegra186_usb2_pad_probe()
555 pad = &usb2->base; in tegra186_usb2_pad_probe()
556 pad->ops = &tegra186_usb2_lane_ops; in tegra186_usb2_pad_probe()
557 pad->soc = soc; in tegra186_usb2_pad_probe()
559 err = tegra_xusb_pad_init(pad, padctl, np); in tegra186_usb2_pad_probe()
565 priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk"); in tegra186_usb2_pad_probe()
566 if (IS_ERR(priv->usb2_trk_clk)) { in tegra186_usb2_pad_probe()
567 err = PTR_ERR(priv->usb2_trk_clk); in tegra186_usb2_pad_probe()
568 dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err); in tegra186_usb2_pad_probe()
576 dev_set_drvdata(&pad->dev, pad); in tegra186_usb2_pad_probe()
581 device_unregister(&pad->dev); in tegra186_usb2_pad_probe()
599 "xusb",
614 return tegra_xusb_find_lane(port->padctl, "usb2", port->index); in tegra186_usb2_port_map()
635 return ERR_PTR(-ENOMEM); in tegra186_usb3_lane_probe()
637 INIT_LIST_HEAD(&usb3->base.list); in tegra186_usb3_lane_probe()
638 usb3->base.soc = &pad->soc->lanes[index]; in tegra186_usb3_lane_probe()
639 usb3->base.index = index; in tegra186_usb3_lane_probe()
640 usb3->base.pad = pad; in tegra186_usb3_lane_probe()
641 usb3->base.np = np; in tegra186_usb3_lane_probe()
643 err = tegra_xusb_lane_parse_dt(&usb3->base, np); in tegra186_usb3_lane_probe()
649 return &usb3->base; in tegra186_usb3_lane_probe()
675 return tegra_xusb_find_lane(port->padctl, "usb3", port->index); in tegra186_usb3_port_map()
689 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_usb3_phy_power_on() local
692 unsigned int index = lane->index; in tegra186_usb3_phy_power_on()
693 struct device *dev = padctl->dev; in tegra186_usb3_phy_power_on()
696 port = tegra_xusb_find_usb3_port(padctl, index); in tegra186_usb3_phy_power_on()
699 return -ENODEV; in tegra186_usb3_phy_power_on()
702 usb2 = tegra_xusb_find_usb2_port(padctl, port->port); in tegra186_usb3_phy_power_on()
706 return -ENODEV; in tegra186_usb3_phy_power_on()
709 mutex_lock(&padctl->lock); in tegra186_usb3_phy_power_on()
711 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP); in tegra186_usb3_phy_power_on()
714 if (usb2->mode == USB_DR_MODE_UNKNOWN) in tegra186_usb3_phy_power_on()
716 else if (usb2->mode == USB_DR_MODE_PERIPHERAL) in tegra186_usb3_phy_power_on()
718 else if (usb2->mode == USB_DR_MODE_HOST) in tegra186_usb3_phy_power_on()
720 else if (usb2->mode == USB_DR_MODE_OTG) in tegra186_usb3_phy_power_on()
723 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP); in tegra186_usb3_phy_power_on()
725 if (padctl->soc->supports_gen2 && port->disable_gen2) { in tegra186_usb3_phy_power_on()
726 value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG); in tegra186_usb3_phy_power_on()
731 padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG); in tegra186_usb3_phy_power_on()
734 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
736 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
740 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
742 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
746 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
748 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_on()
750 mutex_unlock(&padctl->lock); in tegra186_usb3_phy_power_on()
758 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra186_usb3_phy_power_off() local
760 unsigned int index = lane->index; in tegra186_usb3_phy_power_off()
761 struct device *dev = padctl->dev; in tegra186_usb3_phy_power_off()
764 port = tegra_xusb_find_usb3_port(padctl, index); in tegra186_usb3_phy_power_off()
767 return -ENODEV; in tegra186_usb3_phy_power_off()
770 mutex_lock(&padctl->lock); in tegra186_usb3_phy_power_off()
772 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
774 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
778 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
780 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
784 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
786 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1); in tegra186_usb3_phy_power_off()
788 mutex_unlock(&padctl->lock); in tegra186_usb3_phy_power_off()
812 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl, in tegra186_usb3_pad_probe() argument
822 return ERR_PTR(-ENOMEM); in tegra186_usb3_pad_probe()
824 pad = &usb3->base; in tegra186_usb3_pad_probe()
825 pad->ops = &tegra186_usb3_lane_ops; in tegra186_usb3_pad_probe()
826 pad->soc = soc; in tegra186_usb3_pad_probe()
828 err = tegra_xusb_pad_init(pad, padctl, np); in tegra186_usb3_pad_probe()
838 dev_set_drvdata(&pad->dev, pad); in tegra186_usb3_pad_probe()
843 device_unregister(&pad->dev); in tegra186_usb3_pad_probe()
861 "xusb",
865 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl) in tegra186_xusb_read_fuse_calibration() argument
867 struct device *dev = padctl->base.dev; in tegra186_xusb_read_fuse_calibration()
872 count = padctl->base.soc->ports.usb2.count; in tegra186_xusb_read_fuse_calibration()
876 return -ENOMEM; in tegra186_xusb_read_fuse_calibration()
880 if (err != -EPROBE_DEFER) in tegra186_xusb_read_fuse_calibration()
892 padctl->calib.hs_curr_level = level; in tegra186_xusb_read_fuse_calibration()
894 padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) & in tegra186_xusb_read_fuse_calibration()
896 padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) & in tegra186_xusb_read_fuse_calibration()
907 padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK; in tegra186_xusb_read_fuse_calibration()
921 return ERR_PTR(-ENOMEM); in tegra186_xusb_padctl_probe()
923 priv->base.dev = dev; in tegra186_xusb_padctl_probe()
924 priv->base.soc = soc; in tegra186_xusb_padctl_probe()
930 return &priv->base; in tegra186_xusb_padctl_probe()
933 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl) in tegra186_xusb_padctl_remove() argument
945 "avdd-pll-erefeut",
946 "avdd-usb",
947 "vclamp-usb",
948 "vddio-hsic",
952 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
953 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
954 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
965 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
966 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
967 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1013 "avdd-usb",
1014 "vclamp-usb",
1018 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2),
1019 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2),
1020 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2),
1021 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2),
1032 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3),
1033 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3),
1034 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3),
1035 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3),
1072 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");