Lines Matching +full:pre +full:- +full:calibration
1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
37 /* DN Resistor calibration code parameters */
85 /* Calibration digital logic parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * struct xpsgtr_phy - representation of a lane
205 * struct xpsgtr_dev - representation of a ZynMP GT device
255 return readl(gtr_dev->serdes + reg); in xpsgtr_read()
260 writel(value, gtr_dev->serdes + reg); in xpsgtr_write()
275 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_read_phy()
276 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_read_phy()
284 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_write_phy()
285 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_write_phy()
293 void __iomem *addr = gtr_phy->dev->serdes in xpsgtr_clr_set_phy()
294 + gtr_phy->lane * PHY_REG_OFFSET + reg; in xpsgtr_clr_set_phy()
307 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_wait_pll_lock()
311 dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n"); in xpsgtr_wait_pll_lock()
321 if (--timeout == 0) { in xpsgtr_wait_pll_lock()
322 ret = -ETIMEDOUT; in xpsgtr_wait_pll_lock()
329 if (ret == -ETIMEDOUT) in xpsgtr_wait_pll_lock()
330 dev_err(gtr_dev->dev, in xpsgtr_wait_pll_lock()
332 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol); in xpsgtr_wait_pll_lock()
337 /* Configure PLL and spread-sprectrum clock. */
343 ssc = gtr_phy->dev->refclk_sscs[gtr_phy->refclk]; in xpsgtr_configure_pll()
344 step_size = ssc->step_size; in xpsgtr_configure_pll()
346 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
347 PLL_FREQ_MASK, ssc->pll_ref_clk); in xpsgtr_configure_pll()
350 if (gtr_phy->refclk != gtr_phy->lane) { in xpsgtr_configure_pll()
352 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane), in xpsgtr_configure_pll()
353 L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk); in xpsgtr_configure_pll()
372 STEPS_0_MASK, ssc->steps & STEPS_0_MASK); in xpsgtr_configure_pll()
377 (ssc->steps >> STEP_SIZE_SHIFT) & STEPS_1_MASK); in xpsgtr_configure_pll()
389 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_lane_set_protocol()
390 u8 protocol = gtr_phy->protocol; in xpsgtr_lane_set_protocol()
392 switch (gtr_phy->lane) { in xpsgtr_lane_set_protocol()
420 /* DP-specific initialization. */
433 /* SATA-specific initialization. */
436 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sata()
440 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET); in xpsgtr_phy_init_sata()
443 /* SGMII-specific initialization. */
446 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init_sgmii()
447 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
448 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane); in xpsgtr_phy_init_sgmii()
457 /* Configure TX de-emphasis and margining for DP. */
458 static void xpsgtr_phy_configure_dp(struct xpsgtr_phy *gtr_phy, unsigned int pre, in xpsgtr_phy_configure_dp() argument
474 xpsgtr_write_phy(gtr_phy, L0_TXPMD_TM_48, voltage_swing[pre][voltage]); in xpsgtr_phy_configure_dp()
475 xpsgtr_write_phy(gtr_phy, L0_TX_ANA_TM_18, pre_emphasis[pre][voltage]); in xpsgtr_phy_configure_dp()
488 * except when gtr_phy->skip_phy_init is false (this happens when FPD is in xpsgtr_phy_init_required()
491 if (gtr_phy->protocol == ICM_PROTOCOL_USB && gtr_phy->skip_phy_init) in xpsgtr_phy_init_required()
499 * out of spec due to a issue in the calibration logic. This is the workaround
504 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_tx_term_fix()
518 * As a part of work around sequence for PMOS calibration fix, in xpsgtr_phy_tx_term_fix()
527 dev_dbg(gtr_dev->dev, "calibrating...\n"); in xpsgtr_phy_tx_term_fix()
535 if (!--timeout) { in xpsgtr_phy_tx_term_fix()
536 dev_err(gtr_dev->dev, "calibration time out\n"); in xpsgtr_phy_tx_term_fix()
537 return -ETIMEDOUT; in xpsgtr_phy_tx_term_fix()
543 dev_dbg(gtr_dev->dev, "calibration done\n"); in xpsgtr_phy_tx_term_fix()
568 struct xpsgtr_dev *gtr_dev = gtr_phy->dev; in xpsgtr_phy_init()
571 mutex_lock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
577 if (gtr_dev->tx_term_fix) { in xpsgtr_phy_init()
582 gtr_dev->tx_term_fix = false; in xpsgtr_phy_init()
589 * Configure the PLL, the lane protocol, and perform protocol-specific in xpsgtr_phy_init()
595 switch (gtr_phy->protocol) { in xpsgtr_phy_init()
610 mutex_unlock(>r_dev->gtr_mutex); in xpsgtr_phy_init()
618 gtr_phy->skip_phy_init = false; in xpsgtr_phy_exit()
633 if (gtr_phy->protocol != ICM_PROTOCOL_DP || in xpsgtr_phy_power_on()
634 gtr_phy->type == XPSGTR_TYPE_DP_0) in xpsgtr_phy_power_on()
644 if (gtr_phy->protocol != ICM_PROTOCOL_DP) in xpsgtr_phy_configure()
647 xpsgtr_phy_configure_dp(gtr_phy, opts->dp.pre[0], opts->dp.voltage[0]); in xpsgtr_phy_configure()
680 gtr_phy->protocol = ICM_PROTOCOL_SATA; in xpsgtr_set_lane_type()
691 gtr_phy->protocol = ICM_PROTOCOL_USB; in xpsgtr_set_lane_type()
702 gtr_phy->protocol = ICM_PROTOCOL_DP; in xpsgtr_set_lane_type()
715 gtr_phy->protocol = ICM_PROTOCOL_PCIE; in xpsgtr_set_lane_type()
728 gtr_phy->protocol = ICM_PROTOCOL_SGMII; in xpsgtr_set_lane_type()
732 return -EINVAL; in xpsgtr_set_lane_type()
736 return -EINVAL; in xpsgtr_set_lane_type()
738 gtr_phy->type = phy_types[phy_instance]; in xpsgtr_set_lane_type()
769 if (args->args_count != 4) { in xpsgtr_xlate()
771 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
778 phy_lane = args->args[0]; in xpsgtr_xlate()
779 if (phy_lane >= ARRAY_SIZE(gtr_dev->phys)) { in xpsgtr_xlate()
781 return ERR_PTR(-ENODEV); in xpsgtr_xlate()
784 gtr_phy = >r_dev->phys[phy_lane]; in xpsgtr_xlate()
785 phy_type = args->args[1]; in xpsgtr_xlate()
786 phy_instance = args->args[2]; in xpsgtr_xlate()
790 dev_err(gtr_dev->dev, "Invalid PHY type and/or instance\n"); in xpsgtr_xlate()
794 refclk = args->args[3]; in xpsgtr_xlate()
795 if (refclk >= ARRAY_SIZE(gtr_dev->refclk_sscs) || in xpsgtr_xlate()
796 !gtr_dev->refclk_sscs[refclk]) { in xpsgtr_xlate()
798 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
801 gtr_phy->refclk = refclk; in xpsgtr_xlate()
808 if (icm_matrix[phy_lane][i] == gtr_phy->type) in xpsgtr_xlate()
809 return gtr_phy->phy; in xpsgtr_xlate()
812 return ERR_PTR(-EINVAL); in xpsgtr_xlate()
824 gtr_dev->saved_icm_cfg0 = xpsgtr_read(gtr_dev, ICM_CFG0); in xpsgtr_suspend()
825 gtr_dev->saved_icm_cfg1 = xpsgtr_read(gtr_dev, ICM_CFG1); in xpsgtr_suspend()
841 if (!gtr_dev->saved_icm_cfg0 && !gtr_dev->saved_icm_cfg1) in xpsgtr_resume()
845 if (icm_cfg0 == gtr_dev->saved_icm_cfg0 && in xpsgtr_resume()
846 icm_cfg1 == gtr_dev->saved_icm_cfg1) in xpsgtr_resume()
852 for (i = 0; i < ARRAY_SIZE(gtr_dev->phys); i++) in xpsgtr_resume()
853 gtr_dev->phys[i].skip_phy_init = skip_phy_init; in xpsgtr_resume()
870 for (refclk = 0; refclk < ARRAY_SIZE(gtr_dev->refclk_sscs); ++refclk) { in xpsgtr_get_ref_clocks()
877 clk = devm_clk_get_optional(gtr_dev->dev, name); in xpsgtr_get_ref_clocks()
879 if (PTR_ERR(clk) != -EPROBE_DEFER) in xpsgtr_get_ref_clocks()
880 dev_err(gtr_dev->dev, in xpsgtr_get_ref_clocks()
897 gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i]; in xpsgtr_get_ref_clocks()
903 dev_err(gtr_dev->dev, in xpsgtr_get_ref_clocks()
906 return -EINVAL; in xpsgtr_get_ref_clocks()
915 struct device_node *np = pdev->dev.of_node; in xpsgtr_probe()
921 gtr_dev = devm_kzalloc(&pdev->dev, sizeof(*gtr_dev), GFP_KERNEL); in xpsgtr_probe()
923 return -ENOMEM; in xpsgtr_probe()
925 gtr_dev->dev = &pdev->dev; in xpsgtr_probe()
928 mutex_init(>r_dev->gtr_mutex); in xpsgtr_probe()
930 if (of_device_is_compatible(np, "xlnx,zynqmp-psgtr")) in xpsgtr_probe()
931 gtr_dev->tx_term_fix = in xpsgtr_probe()
932 of_property_read_bool(np, "xlnx,tx-termination-fix"); in xpsgtr_probe()
935 gtr_dev->serdes = devm_platform_ioremap_resource_byname(pdev, "serdes"); in xpsgtr_probe()
936 if (IS_ERR(gtr_dev->serdes)) in xpsgtr_probe()
937 return PTR_ERR(gtr_dev->serdes); in xpsgtr_probe()
939 gtr_dev->siou = devm_platform_ioremap_resource_byname(pdev, "siou"); in xpsgtr_probe()
940 if (IS_ERR(gtr_dev->siou)) in xpsgtr_probe()
941 return PTR_ERR(gtr_dev->siou); in xpsgtr_probe()
948 for (port = 0; port < ARRAY_SIZE(gtr_dev->phys); ++port) { in xpsgtr_probe()
949 struct xpsgtr_phy *gtr_phy = >r_dev->phys[port]; in xpsgtr_probe()
952 gtr_phy->lane = port; in xpsgtr_probe()
953 gtr_phy->dev = gtr_dev; in xpsgtr_probe()
955 phy = devm_phy_create(&pdev->dev, np, &xpsgtr_phyops); in xpsgtr_probe()
957 dev_err(&pdev->dev, "failed to create PHY\n"); in xpsgtr_probe()
961 gtr_phy->phy = phy; in xpsgtr_probe()
966 provider = devm_of_phy_provider_register(&pdev->dev, xpsgtr_xlate); in xpsgtr_probe()
968 dev_err(&pdev->dev, "registering provider failed\n"); in xpsgtr_probe()
975 { .compatible = "xlnx,zynqmp-psgtr", },
976 { .compatible = "xlnx,zynqmp-psgtr-v1.1", },
984 .name = "xilinx-psgtr",