Lines Matching +full:ena +full:- +full:gpios
1 // SPDX-License-Identifier: GPL-2.0
25 #include <linux/pinctrl/pinconf-generic.h>
27 #include "pinctrl-intel.h"
177 * Lynxpoint gpios are controlled through both bitmapped registers and
179 * 3 x 32bit registers to cover all 95 GPIOs
182 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
187 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
188 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
189 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
204 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
213 for (i = 0; i < lg->ncommunities; i++) { in lp_get_community()
214 comm = &lg->communities[i]; in lp_get_community()
215 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base) in lp_get_community()
233 offset -= comm->pin_base; in lp_gpio_reg()
242 return comm->regs + reg_offset + reg; in lp_gpio_reg()
249 acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED); in lp_gpio_acpi_use()
264 return !!(value & BIT(offset - 8 + 0)); in lp_gpio_ioxapic_use()
266 return !!(value & BIT(offset - 13 + 3)); in lp_gpio_ioxapic_use()
268 return !!(value & BIT(offset - 45 + 5)); in lp_gpio_ioxapic_use()
277 return lg->soc->ngroups; in lp_get_groups_count()
285 return lg->soc->groups[selector].name; in lp_get_group_name()
295 *pins = lg->soc->groups[selector].pins; in lp_get_group_pins()
296 *num_pins = lg->soc->groups[selector].npins; in lp_get_group_pins()
305 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_pin_dbg_show()
306 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_dbg_show()
334 return lg->soc->nfunctions; in lp_get_functions_count()
342 return lg->soc->functions[selector].name; in lp_get_function_name()
352 *groups = lg->soc->functions[selector].groups; in lp_get_function_groups()
353 *num_groups = lg->soc->functions[selector].ngroups; in lp_get_function_groups()
362 const struct intel_pingroup *grp = &lg->soc->groups[group]; in lp_pinmux_set_mux()
366 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pinmux_set_mux()
369 for (i = 0; i < grp->npins; i++) { in lp_pinmux_set_mux()
370 void __iomem *reg = lp_gpio_reg(&lg->chip, grp->pins[i], LP_CONFIG1); in lp_pinmux_set_mux()
376 if (grp->modes) in lp_pinmux_set_mux()
377 value |= grp->modes[i]; in lp_pinmux_set_mux()
379 value |= grp->mode; in lp_pinmux_set_mux()
384 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pinmux_set_mux()
404 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_request_enable()
405 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_request_enable()
409 pm_runtime_get(lg->dev); in lp_gpio_request_enable()
411 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_request_enable()
420 dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin); in lp_gpio_request_enable()
426 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_request_enable()
436 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_gpio_disable_free()
439 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_disable_free()
444 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_disable_free()
446 pm_runtime_put(lg->dev); in lp_gpio_disable_free()
454 void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1); in lp_gpio_set_direction()
458 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_set_direction()
471 WARN(lp_gpio_ioxapic_use(&lg->chip, pin), in lp_gpio_set_direction()
476 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_set_direction()
495 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_get()
501 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pin_config_get()
503 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pin_config_get()
510 return -EINVAL; in lp_pin_config_get()
514 return -EINVAL; in lp_pin_config_get()
520 return -EINVAL; in lp_pin_config_get()
525 return -ENOTSUPP; in lp_pin_config_get()
537 void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2); in lp_pin_config_set()
543 raw_spin_lock_irqsave(&lg->lock, flags); in lp_pin_config_set()
563 ret = -ENOTSUPP; in lp_pin_config_set()
573 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_pin_config_set()
603 raw_spin_lock_irqsave(&lg->lock, flags); in lp_gpio_set()
610 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_gpio_set()
615 return pinctrl_gpio_direction_input(chip->base + offset); in lp_gpio_direction_input()
623 return pinctrl_gpio_direction_output(chip->base + offset); in lp_gpio_direction_output()
642 void __iomem *reg, *ena; in lp_gpio_irq_handler() local
647 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_handler()
648 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_handler()
649 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_handler()
652 pending = ioread32(reg) & ioread32(ena); in lp_gpio_irq_handler()
657 irq = irq_find_mapping(lg->chip.irq.domain, base + pin); in lp_gpio_irq_handler()
661 chip->irq_eoi(data); in lp_gpio_irq_handler()
669 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT); in lp_irq_ack()
672 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_ack()
674 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_ack()
690 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_enable()
693 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_enable()
695 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_enable()
703 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_disable()
706 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_disable()
708 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_disable()
716 void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); in lp_irq_set_type()
720 if (hwirq >= lg->chip.ngpio) in lp_irq_set_type()
721 return -EINVAL; in lp_irq_set_type()
725 dev_err(lg->dev, "pin %u can't be used as IRQ\n", hwirq); in lp_irq_set_type()
726 return -EBUSY; in lp_irq_set_type()
729 raw_spin_lock_irqsave(&lg->lock, flags); in lp_irq_set_type()
755 raw_spin_unlock_irqrestore(&lg->lock, flags); in lp_irq_set_type()
761 .name = "LP-GPIO",
777 for (base = 0; base < lg->chip.ngpio; base += 32) { in lp_gpio_irq_init_hw()
779 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE); in lp_gpio_irq_init_hw()
782 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT); in lp_gpio_irq_init_hw()
792 struct device *dev = lg->dev; in lp_gpio_add_pin_ranges()
795 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins); in lp_gpio_add_pin_ranges()
807 struct device *dev = &pdev->dev; in lp_gpio_probe()
815 return -ENODEV; in lp_gpio_probe()
819 return -ENOMEM; in lp_gpio_probe()
821 lg->dev = dev; in lp_gpio_probe()
822 lg->soc = soc; in lp_gpio_probe()
824 lg->ncommunities = lg->soc->ncommunities; in lp_gpio_probe()
825 lg->communities = devm_kcalloc(dev, lg->ncommunities, in lp_gpio_probe()
826 sizeof(*lg->communities), GFP_KERNEL); in lp_gpio_probe()
827 if (!lg->communities) in lp_gpio_probe()
828 return -ENOMEM; in lp_gpio_probe()
830 lg->pctldesc = lptlp_pinctrl_desc; in lp_gpio_probe()
831 lg->pctldesc.name = dev_name(dev); in lp_gpio_probe()
832 lg->pctldesc.pins = lg->soc->pins; in lp_gpio_probe()
833 lg->pctldesc.npins = lg->soc->npins; in lp_gpio_probe()
835 lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg); in lp_gpio_probe()
836 if (IS_ERR(lg->pctldev)) { in lp_gpio_probe()
838 return PTR_ERR(lg->pctldev); in lp_gpio_probe()
846 return -EINVAL; in lp_gpio_probe()
849 regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc)); in lp_gpio_probe()
852 return -EBUSY; in lp_gpio_probe()
855 for (i = 0; i < lg->soc->ncommunities; i++) { in lp_gpio_probe()
856 struct intel_community *comm = &lg->communities[i]; in lp_gpio_probe()
858 *comm = lg->soc->communities[i]; in lp_gpio_probe()
860 comm->regs = regs; in lp_gpio_probe()
861 comm->pad_regs = regs + 0x100; in lp_gpio_probe()
864 raw_spin_lock_init(&lg->lock); in lp_gpio_probe()
866 gc = &lg->chip; in lp_gpio_probe()
867 gc->label = dev_name(dev); in lp_gpio_probe()
868 gc->owner = THIS_MODULE; in lp_gpio_probe()
869 gc->request = gpiochip_generic_request; in lp_gpio_probe()
870 gc->free = gpiochip_generic_free; in lp_gpio_probe()
871 gc->direction_input = lp_gpio_direction_input; in lp_gpio_probe()
872 gc->direction_output = lp_gpio_direction_output; in lp_gpio_probe()
873 gc->get = lp_gpio_get; in lp_gpio_probe()
874 gc->set = lp_gpio_set; in lp_gpio_probe()
875 gc->get_direction = lp_gpio_get_direction; in lp_gpio_probe()
876 gc->base = -1; in lp_gpio_probe()
877 gc->ngpio = LP_NUM_GPIO; in lp_gpio_probe()
878 gc->can_sleep = false; in lp_gpio_probe()
879 gc->add_pin_ranges = lp_gpio_add_pin_ranges; in lp_gpio_probe()
880 gc->parent = dev; in lp_gpio_probe()
887 girq = &gc->irq; in lp_gpio_probe()
888 girq->chip = &lp_irqchip; in lp_gpio_probe()
889 girq->init_hw = lp_gpio_irq_init_hw; in lp_gpio_probe()
890 girq->parent_handler = lp_gpio_irq_handler; in lp_gpio_probe()
891 girq->num_parents = 1; in lp_gpio_probe()
892 girq->parents = devm_kcalloc(dev, girq->num_parents, in lp_gpio_probe()
893 sizeof(*girq->parents), in lp_gpio_probe()
895 if (!girq->parents) in lp_gpio_probe()
896 return -ENOMEM; in lp_gpio_probe()
897 girq->parents[0] = irq; in lp_gpio_probe()
898 girq->default_type = IRQ_TYPE_NONE; in lp_gpio_probe()
899 girq->handler = handle_bad_irq; in lp_gpio_probe()
904 dev_err(dev, "failed adding lp-gpio chip\n"); in lp_gpio_probe()
915 pm_runtime_disable(&pdev->dev); in lp_gpio_remove()
932 struct gpio_chip *chip = &lg->chip; in lp_gpio_resume()
936 /* on some hardware suspend clears input sensing, re-enable it here */ in lp_gpio_resume()