Lines Matching +full:dev +full:- +full:a +full:- +full:active +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0-only
9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
33 #include <linux/pinctrl/pinconf-generic.h>
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_get_direction()
46 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_direction()
47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_get_direction()
61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_direction_input()
62 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_input()
64 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_input()
65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_direction_input()
77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_direction_output()
78 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_direction_output()
84 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_direction_output()
85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_direction_output()
96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_get_value()
97 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_get_value()
98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_get_value()
109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_set_value()
110 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_value()
115 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_value()
116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_set_value()
128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_set_debounce()
132 pin_reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_set_debounce()
137 pin_reg = readl(gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
178 ret = -EINVAL; in amd_gpio_set_debounce()
186 writel(pin_reg, gpio_dev->base + offset * 4); in amd_gpio_set_debounce()
187 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_set_debounce()
214 seq_printf(s, "WAKE_INT_MASTER_REG: 0x%08x\n", readl(gpio_dev->base + WAKE_INT_MASTER_REG)); in amd_gpio_dbg_show()
215 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { in amd_gpio_dbg_show()
241 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_dbg_show()
242 pin_reg = readl(gpio_dev->base + i * 4); in amd_gpio_dbg_show()
243 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_dbg_show()
251 active_level = "Active high|"; in amd_gpio_dbg_show()
253 active_level = "Active low|"; in amd_gpio_dbg_show()
256 active_level = "Active on both|"; in amd_gpio_dbg_show()
258 active_level = "Unknown Active level|"; in amd_gpio_dbg_show()
295 pull_up_enable = "pull-up is enabled|"; in amd_gpio_dbg_show()
297 pull_up_sel = "8k pull-up|"; in amd_gpio_dbg_show()
299 pull_up_sel = "4k pull-up|"; in amd_gpio_dbg_show()
301 pull_up_enable = "pull-up is disabled|"; in amd_gpio_dbg_show()
306 pull_down_enable = "pull-down is enabled|"; in amd_gpio_dbg_show()
308 pull_down_enable = "Pull-down is disabled|"; in amd_gpio_dbg_show()
348 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_enable()
349 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
352 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_enable()
353 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_enable()
363 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_disable()
364 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_disable()
368 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_disable()
378 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_mask()
379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_mask()
382 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_mask()
392 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_unmask()
393 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
395 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_unmask()
396 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_unmask()
406 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_eoi()
407 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_eoi()
409 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_eoi()
410 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_eoi()
421 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_set_type()
422 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
464 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); in amd_gpio_irq_set_type()
465 ret = -EINVAL; in amd_gpio_irq_set_type()
470 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the in amd_gpio_irq_set_type()
472 * generation for *all* GPIOs for a length of time that depends on in amd_gpio_irq_set_type()
488 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
489 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) in amd_gpio_irq_set_type()
491 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); in amd_gpio_irq_set_type()
492 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_set_type()
523 struct gpio_chip *gc = &gpio_dev->gc; in amd_gpio_irq_handler()
532 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
533 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); in amd_gpio_irq_handler()
535 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); in amd_gpio_irq_handler()
536 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
538 /* Bit 0-45 contain the relevant status bits */ in amd_gpio_irq_handler()
539 status &= (1ULL << 46) - 1; in amd_gpio_irq_handler()
540 regs = gpio_dev->base; in amd_gpio_irq_handler()
546 /* Each status bit covers four pins */ in amd_gpio_irq_handler()
552 irq = irq_find_mapping(gc->irq.domain, irqnr + i); in amd_gpio_irq_handler()
560 * If we didn't find a mapping for the interrupt, in amd_gpio_irq_handler()
561 * disable it in order to avoid a system hang caused in amd_gpio_irq_handler()
564 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
568 dev_dbg(&gpio_dev->pdev->dev, in amd_gpio_irq_handler()
573 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
579 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
580 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_handler()
582 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); in amd_gpio_irq_handler()
583 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_handler()
592 return gpio_dev->ngroups; in amd_get_groups_count()
600 return gpio_dev->groups[group].name; in amd_get_group_name()
605 const unsigned **pins, in amd_get_group_pins() argument
610 *pins = gpio_dev->groups[group].pins; in amd_get_group_pins()
611 *num_pins = gpio_dev->groups[group].npins; in amd_get_group_pins()
635 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_pinconf_get()
636 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_get()
637 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_pinconf_get()
656 dev_dbg(&gpio_dev->pdev->dev, "Invalid config param %04x\n", in amd_pinconf_get()
658 return -ENOTSUPP; in amd_pinconf_get()
677 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_pinconf_set()
681 pin_reg = readl(gpio_dev->base + pin*4); in amd_pinconf_set()
709 dev_dbg(&gpio_dev->pdev->dev, in amd_pinconf_set()
711 ret = -ENOTSUPP; in amd_pinconf_set()
714 writel(pin_reg, gpio_dev->base + pin*4); in amd_pinconf_set()
716 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_pinconf_set()
725 const unsigned *pins; in amd_pinconf_group_get() local
729 ret = amd_get_group_pins(pctldev, group, &pins, &npins); in amd_pinconf_group_get()
733 if (amd_pinconf_get(pctldev, pins[0], config)) in amd_pinconf_group_get()
734 return -ENOTSUPP; in amd_pinconf_group_get()
743 const unsigned *pins; in amd_pinconf_group_set() local
747 ret = amd_get_group_pins(pctldev, group, &pins, &npins); in amd_pinconf_group_set()
751 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) in amd_pinconf_group_set()
752 return -ENOTSUPP; in amd_pinconf_group_set()
768 return amd_pinconf_set(gpio_dev->pctrl, pin, &config, 1); in amd_gpio_set_config()
780 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_irq_init()
789 for (i = 0; i < desc->npins; i++) { in amd_gpio_irq_init()
790 int pin = desc->pins[i].number; in amd_gpio_irq_init()
791 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); in amd_gpio_irq_init()
796 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_irq_init()
798 pin_reg = readl(gpio_dev->base + pin * 4); in amd_gpio_irq_init()
800 writel(pin_reg, gpio_dev->base + pin * 4); in amd_gpio_irq_init()
802 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_irq_init()
809 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); in amd_gpio_should_save()
818 if (pd->mux_owner || pd->gpio_owner || in amd_gpio_should_save()
819 gpiochip_line_is_irq(&gpio_dev->gc, pin)) in amd_gpio_should_save()
825 static int amd_gpio_suspend(struct device *dev) in amd_gpio_suspend() argument
827 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); in amd_gpio_suspend()
828 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_suspend()
832 for (i = 0; i < desc->npins; i++) { in amd_gpio_suspend()
833 int pin = desc->pins[i].number; in amd_gpio_suspend()
838 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_suspend()
839 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; in amd_gpio_suspend()
840 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_suspend()
846 static int amd_gpio_resume(struct device *dev) in amd_gpio_resume() argument
848 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); in amd_gpio_resume()
849 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; in amd_gpio_resume()
853 for (i = 0; i < desc->npins; i++) { in amd_gpio_resume()
854 int pin = desc->pins[i].number; in amd_gpio_resume()
859 raw_spin_lock_irqsave(&gpio_dev->lock, flags); in amd_gpio_resume()
860 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; in amd_gpio_resume()
861 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); in amd_gpio_resume()
862 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); in amd_gpio_resume()
875 .pins = kerncz_pins,
890 gpio_dev = devm_kzalloc(&pdev->dev, in amd_gpio_probe()
893 return -ENOMEM; in amd_gpio_probe()
895 raw_spin_lock_init(&gpio_dev->lock); in amd_gpio_probe()
899 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); in amd_gpio_probe()
900 return -EINVAL; in amd_gpio_probe()
903 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, in amd_gpio_probe()
905 if (!gpio_dev->base) in amd_gpio_probe()
906 return -ENOMEM; in amd_gpio_probe()
913 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, in amd_gpio_probe()
914 sizeof(*gpio_dev->saved_regs), in amd_gpio_probe()
916 if (!gpio_dev->saved_regs) in amd_gpio_probe()
917 return -ENOMEM; in amd_gpio_probe()
920 gpio_dev->pdev = pdev; in amd_gpio_probe()
921 gpio_dev->gc.get_direction = amd_gpio_get_direction; in amd_gpio_probe()
922 gpio_dev->gc.direction_input = amd_gpio_direction_input; in amd_gpio_probe()
923 gpio_dev->gc.direction_output = amd_gpio_direction_output; in amd_gpio_probe()
924 gpio_dev->gc.get = amd_gpio_get_value; in amd_gpio_probe()
925 gpio_dev->gc.set = amd_gpio_set_value; in amd_gpio_probe()
926 gpio_dev->gc.set_config = amd_gpio_set_config; in amd_gpio_probe()
927 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; in amd_gpio_probe()
929 gpio_dev->gc.base = -1; in amd_gpio_probe()
930 gpio_dev->gc.label = pdev->name; in amd_gpio_probe()
931 gpio_dev->gc.owner = THIS_MODULE; in amd_gpio_probe()
932 gpio_dev->gc.parent = &pdev->dev; in amd_gpio_probe()
933 gpio_dev->gc.ngpio = resource_size(res) / 4; in amd_gpio_probe()
935 gpio_dev->gc.of_node = pdev->dev.of_node; in amd_gpio_probe()
938 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; in amd_gpio_probe()
939 gpio_dev->groups = kerncz_groups; in amd_gpio_probe()
940 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); in amd_gpio_probe()
942 amd_pinctrl_desc.name = dev_name(&pdev->dev); in amd_gpio_probe()
943 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, in amd_gpio_probe()
945 if (IS_ERR(gpio_dev->pctrl)) { in amd_gpio_probe()
946 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); in amd_gpio_probe()
947 return PTR_ERR(gpio_dev->pctrl); in amd_gpio_probe()
953 girq = &gpio_dev->gc.irq; in amd_gpio_probe()
954 girq->chip = &amd_gpio_irqchip; in amd_gpio_probe()
956 girq->parent_handler = NULL; in amd_gpio_probe()
957 girq->num_parents = 0; in amd_gpio_probe()
958 girq->parents = NULL; in amd_gpio_probe()
959 girq->default_type = IRQ_TYPE_NONE; in amd_gpio_probe()
960 girq->handler = handle_simple_irq; in amd_gpio_probe()
962 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); in amd_gpio_probe()
966 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), in amd_gpio_probe()
967 0, 0, gpio_dev->gc.ngpio); in amd_gpio_probe()
969 dev_err(&pdev->dev, "Failed to add pin range\n"); in amd_gpio_probe()
973 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, in amd_gpio_probe()
980 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); in amd_gpio_probe()
984 gpiochip_remove(&gpio_dev->gc); in amd_gpio_probe()
995 gpiochip_remove(&gpio_dev->gc); in amd_gpio_remove()