Lines Matching +full:pin +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
26 #include "pinctrl-at91.h"
95 * struct at91_pmx_func - describes AT91 pinmux functions
97 * @groups: corresponding pin groups
115 * struct at91_pmx_pin - describes an At91 pin mux
116 * @bank: the bank of the pin
117 * @pin: the pin number in the @bank
118 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
119 * @conf: the configuration of the pin: PULL_UP, MULTIDRIVE etc...
123 uint32_t pin; member
124 enum at91_mux mux; member
129 * struct at91_pin_group - describes an At91 pin group
130 * @name: the name of this specific pin group
131 * @pins_conf: the mux mode for each pin in this group. The size of this
134 * from the driver-local pin enumeration space
146 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
147 * on new IP with support for periph C and D the way to mux in
152 * @mux_A_periph: mux as periph A
153 * @mux_B_periph: mux as periph B
154 * @mux_C_periph: mux as periph C
155 * @mux_D_periph: mux as periph D
176 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
178 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
180 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
182 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
184 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
185 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
187 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
188 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
221 for (i = 0; i < info->ngroups; i++) { in at91_pinctrl_find_group_by_name()
222 if (strcmp(info->groups[i].name, name)) in at91_pinctrl_find_group_by_name()
225 grp = &info->groups[i]; in at91_pinctrl_find_group_by_name()
226 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); in at91_pinctrl_find_group_by_name()
237 return info->ngroups; in at91_get_groups_count()
245 return info->groups[selector].name; in at91_get_group_name()
254 if (selector >= info->ngroups) in at91_get_group_pins()
255 return -EINVAL; in at91_get_group_pins()
257 *pins = info->groups[selector].pins; in at91_get_group_pins()
258 *npins = info->groups[selector].npins; in at91_get_group_pins()
266 seq_printf(s, "%s", dev_name(pctldev->dev)); in at91_pin_dbg_show()
284 grp = at91_pinctrl_find_group_by_name(info, np->name); in at91_dt_node_to_map()
286 dev_err(info->dev, "unable to find group for node %pOFn\n", in at91_dt_node_to_map()
288 return -EINVAL; in at91_dt_node_to_map()
291 map_num += grp->npins; in at91_dt_node_to_map()
292 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), in at91_dt_node_to_map()
295 return -ENOMEM; in at91_dt_node_to_map()
300 /* create mux map */ in at91_dt_node_to_map()
303 devm_kfree(pctldev->dev, new_map); in at91_dt_node_to_map()
304 return -EINVAL; in at91_dt_node_to_map()
307 new_map[0].data.mux.function = parent->name; in at91_dt_node_to_map()
308 new_map[0].data.mux.group = np->name; in at91_dt_node_to_map()
313 for (i = 0; i < grp->npins; i++) { in at91_dt_node_to_map()
316 pin_get_name(pctldev, grp->pins[i]); in at91_dt_node_to_map()
317 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; in at91_dt_node_to_map()
321 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in at91_dt_node_to_map()
322 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in at91_dt_node_to_map()
347 return gpio_chips[bank]->regbase; in pin_to_controller()
350 static inline int pin_to_bank(unsigned pin) in pin_to_bank() argument
352 return pin /= MAX_NB_GPIO_PER_BANK; in pin_to_bank()
355 static unsigned pin_to_mask(unsigned int pin) in pin_to_mask() argument
357 return 1 << pin; in pin_to_mask()
360 static unsigned two_bit_pin_value_shift_amount(unsigned int pin) in two_bit_pin_value_shift_amount() argument
362 /* return the shift value for a pin for "two bit" per pin registers, in two_bit_pin_value_shift_amount()
364 return 2*((pin >= MAX_NB_GPIO_PER_BANK/2) in two_bit_pin_value_shift_amount()
365 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); in two_bit_pin_value_shift_amount()
368 static unsigned sama5d3_get_drive_register(unsigned int pin) in sama5d3_get_drive_register() argument
371 * with two bits per pin */ in sama5d3_get_drive_register()
372 return (pin >= MAX_NB_GPIO_PER_BANK/2) in sama5d3_get_drive_register()
376 static unsigned at91sam9x5_get_drive_register(unsigned int pin) in at91sam9x5_get_drive_register() argument
379 * with two bits per pin */ in at91sam9x5_get_drive_register()
380 return (pin >= MAX_NB_GPIO_PER_BANK/2) in at91sam9x5_get_drive_register()
389 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) in at91_mux_get_pullup() argument
391 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); in at91_mux_get_pullup()
402 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) in at91_mux_get_output() argument
404 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; in at91_mux_get_output()
405 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; in at91_mux_get_output()
415 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) in at91_mux_get_multidrive() argument
417 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; in at91_mux_get_multidrive()
489 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_get_deglitch() argument
491 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; in at91_mux_get_deglitch()
499 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_deglitch() argument
501 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) in at91_mux_pio3_get_deglitch()
502 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_deglitch()
514 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) in at91_mux_pio3_get_debounce() argument
518 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && in at91_mux_pio3_get_debounce()
519 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_debounce()
533 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_pulldown() argument
535 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); in at91_mux_pio3_get_pulldown()
551 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_schmitt_trig() argument
553 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; in at91_mux_pio3_get_schmitt_trig()
556 static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) in read_drive_strength() argument
560 tmp = tmp >> two_bit_pin_value_shift_amount(pin); in read_drive_strength()
566 unsigned pin) in at91_mux_sama5d3_get_drivestrength() argument
569 sama5d3_get_drive_register(pin), pin); in at91_mux_sama5d3_get_drivestrength()
580 unsigned pin) in at91_mux_sam9x5_get_drivestrength() argument
583 at91sam9x5_get_drive_register(pin), pin); in at91_mux_sam9x5_get_drivestrength()
587 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; in at91_mux_sam9x5_get_drivestrength()
593 unsigned pin) in at91_mux_sam9x60_get_drivestrength() argument
597 if (tmp & BIT(pin)) in at91_mux_sam9x60_get_drivestrength()
603 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) in at91_mux_sam9x60_get_slewrate() argument
607 if ((tmp & BIT(pin))) in at91_mux_sam9x60_get_slewrate()
613 static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) in set_drive_strength() argument
616 unsigned shift = two_bit_pin_value_shift_amount(pin); in set_drive_strength()
624 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sama5d3_set_drivestrength() argument
632 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); in at91_mux_sama5d3_set_drivestrength()
635 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x5_set_drivestrength() argument
644 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; in at91_mux_sam9x5_set_drivestrength()
646 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, in at91_mux_sam9x5_set_drivestrength()
650 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_drivestrength() argument
664 tmp &= ~BIT(pin); in at91_mux_sam9x60_set_drivestrength()
666 tmp |= BIT(pin); in at91_mux_sam9x60_set_drivestrength()
671 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_slewrate() argument
682 tmp &= ~BIT(pin); in at91_mux_sam9x60_set_slewrate()
684 tmp |= BIT(pin); in at91_mux_sam9x60_set_slewrate()
757 static void at91_pin_dbg(const struct device *dev, const struct at91_pmx_pin *pin) in at91_pin_dbg() argument
759 if (pin->mux) { in at91_pin_dbg()
761 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); in at91_pin_dbg()
764 pin->bank + 'A', pin->pin, pin->conf); in at91_pin_dbg()
769 int index, const struct at91_pmx_pin *pin) in pin_check_config() argument
771 int mux; in pin_check_config() local
774 if (pin->bank >= gpio_banks) { in pin_check_config()
775 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", in pin_check_config()
776 name, index, pin->bank, gpio_banks); in pin_check_config()
777 return -EINVAL; in pin_check_config()
780 if (!gpio_chips[pin->bank]) { in pin_check_config()
781 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", in pin_check_config()
782 name, index, pin->bank); in pin_check_config()
783 return -ENXIO; in pin_check_config()
786 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { in pin_check_config()
787 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", in pin_check_config()
788 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); in pin_check_config()
789 return -EINVAL; in pin_check_config()
792 if (!pin->mux) in pin_check_config()
795 mux = pin->mux - 1; in pin_check_config()
797 if (mux >= info->nmux) { in pin_check_config()
798 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", in pin_check_config()
799 name, index, mux, info->nmux); in pin_check_config()
800 return -EINVAL; in pin_check_config()
803 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { in pin_check_config()
804 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", in pin_check_config()
805 name, index, mux, pin->bank + 'A', pin->pin); in pin_check_config()
806 return -EINVAL; in pin_check_config()
827 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; in at91_pmx_set()
828 const struct at91_pmx_pin *pin; in at91_pmx_set() local
829 uint32_t npins = info->groups[group].npins; in at91_pmx_set()
834 dev_dbg(info->dev, "enable function %s group %s\n", in at91_pmx_set()
835 info->functions[selector].name, info->groups[group].name); in at91_pmx_set()
840 pin = &pins_conf[i]; in at91_pmx_set()
841 ret = pin_check_config(info, info->groups[group].name, i, pin); in at91_pmx_set()
847 pin = &pins_conf[i]; in at91_pmx_set()
848 at91_pin_dbg(info->dev, pin); in at91_pmx_set()
849 pio = pin_to_controller(info, pin->bank); in at91_pmx_set()
854 mask = pin_to_mask(pin->pin); in at91_pmx_set()
856 switch (pin->mux) { in at91_pmx_set()
861 info->ops->mux_A_periph(pio, mask); in at91_pmx_set()
864 info->ops->mux_B_periph(pio, mask); in at91_pmx_set()
867 if (!info->ops->mux_C_periph) in at91_pmx_set()
868 return -EINVAL; in at91_pmx_set()
869 info->ops->mux_C_periph(pio, mask); in at91_pmx_set()
872 if (!info->ops->mux_D_periph) in at91_pmx_set()
873 return -EINVAL; in at91_pmx_set()
874 info->ops->mux_D_periph(pio, mask); in at91_pmx_set()
877 if (pin->mux) in at91_pmx_set()
888 return info->nfunctions; in at91_pmx_get_funcs_count()
896 return info->functions[selector].name; in at91_pmx_get_func_name()
905 *groups = info->functions[selector].groups; in at91_pmx_get_groups()
906 *num_groups = info->functions[selector].ngroups; in at91_pmx_get_groups()
921 dev_err(npct->dev, "invalid range\n"); in at91_gpio_request_enable()
922 return -EINVAL; in at91_gpio_request_enable()
924 if (!range->gc) { in at91_gpio_request_enable()
925 dev_err(npct->dev, "missing GPIO chip in range\n"); in at91_gpio_request_enable()
926 return -EINVAL; in at91_gpio_request_enable()
928 chip = range->gc; in at91_gpio_request_enable()
931 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); in at91_gpio_request_enable()
933 mask = 1 << (offset - chip->base); in at91_gpio_request_enable()
935 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", in at91_gpio_request_enable()
936 offset, 'A' + range->id, offset - chip->base, mask); in at91_gpio_request_enable()
938 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
949 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); in at91_gpio_disable_free()
950 /* Set the pin to some default state, GPIO is usually default */ in at91_gpio_disable_free()
967 unsigned pin; in at91_pinconf_get() local
972 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); in at91_pinconf_get()
976 return -EINVAL; in at91_pinconf_get()
978 pin = pin_id % MAX_NB_GPIO_PER_BANK; in at91_pinconf_get()
980 if (at91_mux_get_multidrive(pio, pin)) in at91_pinconf_get()
983 if (at91_mux_get_pullup(pio, pin)) in at91_pinconf_get()
986 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) in at91_pinconf_get()
988 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) in at91_pinconf_get()
990 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) in at91_pinconf_get()
992 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) in at91_pinconf_get()
994 if (info->ops->get_drivestrength) in at91_pinconf_get()
995 *config |= (info->ops->get_drivestrength(pio, pin) in at91_pinconf_get()
997 if (info->ops->get_slewrate) in at91_pinconf_get()
998 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); in at91_pinconf_get()
999 if (at91_mux_get_output(pio, pin, &out)) in at91_pinconf_get()
1014 unsigned pin; in at91_pinconf_set() local
1019 dev_dbg(info->dev, in at91_pinconf_set()
1025 return -EINVAL; in at91_pinconf_set()
1027 pin = pin_id % MAX_NB_GPIO_PER_BANK; in at91_pinconf_set()
1028 mask = pin_to_mask(pin); in at91_pinconf_set()
1031 return -EINVAL; in at91_pinconf_set()
1037 if (info->ops->set_deglitch) in at91_pinconf_set()
1038 info->ops->set_deglitch(pio, mask, config & DEGLITCH); in at91_pinconf_set()
1039 if (info->ops->set_debounce) in at91_pinconf_set()
1040 info->ops->set_debounce(pio, mask, config & DEBOUNCE, in at91_pinconf_set()
1042 if (info->ops->set_pulldown) in at91_pinconf_set()
1043 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); in at91_pinconf_set()
1044 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) in at91_pinconf_set()
1045 info->ops->disable_schmitt_trig(pio, mask); in at91_pinconf_set()
1046 if (info->ops->set_drivestrength) in at91_pinconf_set()
1047 info->ops->set_drivestrength(pio, pin, in at91_pinconf_set()
1050 if (info->ops->set_slewrate) in at91_pinconf_set()
1051 info->ops->set_slewrate(pio, pin, in at91_pinconf_set()
1125 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1135 info->nactive_banks++; in at91_pinctrl_child_count()
1137 info->nfunctions++; in at91_pinctrl_child_count()
1138 info->ngroups += of_get_child_count(child); in at91_pinctrl_child_count()
1150 list = of_get_property(np, "atmel,mux-mask", &size); in at91_pinctrl_mux_mask()
1152 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1153 return -EINVAL; in at91_pinctrl_mux_mask()
1158 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); in at91_pinctrl_mux_mask()
1159 return -EINVAL; in at91_pinctrl_mux_mask()
1161 info->nmux = size / gpio_banks; in at91_pinctrl_mux_mask()
1163 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), in at91_pinctrl_mux_mask()
1165 if (!info->mux_mask) in at91_pinctrl_mux_mask()
1166 return -ENOMEM; in at91_pinctrl_mux_mask()
1168 ret = of_property_read_u32_array(np, "atmel,mux-mask", in at91_pinctrl_mux_mask()
1169 info->mux_mask, size); in at91_pinctrl_mux_mask()
1171 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1179 struct at91_pmx_pin *pin; in at91_pinctrl_parse_groups() local
1184 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in at91_pinctrl_parse_groups()
1187 grp->name = np->name; in at91_pinctrl_parse_groups()
1190 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, in at91_pinctrl_parse_groups()
1197 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in at91_pinctrl_parse_groups()
1198 return -EINVAL; in at91_pinctrl_parse_groups()
1201 grp->npins = size / 4; in at91_pinctrl_parse_groups()
1202 pin = grp->pins_conf = devm_kcalloc(info->dev, in at91_pinctrl_parse_groups()
1203 grp->npins, in at91_pinctrl_parse_groups()
1206 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in at91_pinctrl_parse_groups()
1208 if (!grp->pins_conf || !grp->pins) in at91_pinctrl_parse_groups()
1209 return -ENOMEM; in at91_pinctrl_parse_groups()
1212 pin->bank = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1213 pin->pin = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1214 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; in at91_pinctrl_parse_groups()
1215 pin->mux = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1216 pin->conf = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1218 at91_pin_dbg(info->dev, pin); in at91_pinctrl_parse_groups()
1219 pin++; in at91_pinctrl_parse_groups()
1235 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in at91_pinctrl_parse_functions()
1237 func = &info->functions[index]; in at91_pinctrl_parse_functions()
1240 func->name = np->name; in at91_pinctrl_parse_functions()
1241 func->ngroups = of_get_child_count(np); in at91_pinctrl_parse_functions()
1242 if (func->ngroups == 0) { in at91_pinctrl_parse_functions()
1243 dev_err(info->dev, "no groups defined\n"); in at91_pinctrl_parse_functions()
1244 return -EINVAL; in at91_pinctrl_parse_functions()
1246 func->groups = devm_kcalloc(info->dev, in at91_pinctrl_parse_functions()
1247 func->ngroups, sizeof(char *), GFP_KERNEL); in at91_pinctrl_parse_functions()
1248 if (!func->groups) in at91_pinctrl_parse_functions()
1249 return -ENOMEM; in at91_pinctrl_parse_functions()
1252 func->groups[i] = child->name; in at91_pinctrl_parse_functions()
1253 grp = &info->groups[grp_index++]; in at91_pinctrl_parse_functions()
1265 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1266 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1267 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1268 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1278 struct device_node *np = pdev->dev.of_node; in at91_pinctrl_probe_dt()
1282 return -ENODEV; in at91_pinctrl_probe_dt()
1284 info->dev = &pdev->dev; in at91_pinctrl_probe_dt()
1285 info->ops = (struct at91_pinctrl_mux_ops *) in at91_pinctrl_probe_dt()
1286 of_match_device(at91_pinctrl_of_match, &pdev->dev)->data; in at91_pinctrl_probe_dt()
1290 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n"); in at91_pinctrl_probe_dt()
1291 return -EINVAL; in at91_pinctrl_probe_dt()
1298 dev_dbg(&pdev->dev, "nmux = %d\n", info->nmux); in at91_pinctrl_probe_dt()
1300 dev_dbg(&pdev->dev, "mux-mask\n"); in at91_pinctrl_probe_dt()
1301 tmp = info->mux_mask; in at91_pinctrl_probe_dt()
1303 for (j = 0; j < info->nmux; j++, tmp++) { in at91_pinctrl_probe_dt()
1304 dev_dbg(&pdev->dev, "%d:%d\t0x%x\n", i, j, tmp[0]); in at91_pinctrl_probe_dt()
1308 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1309 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1310 info->functions = devm_kcalloc(&pdev->dev, in at91_pinctrl_probe_dt()
1311 info->nfunctions, in at91_pinctrl_probe_dt()
1314 if (!info->functions) in at91_pinctrl_probe_dt()
1315 return -ENOMEM; in at91_pinctrl_probe_dt()
1317 info->groups = devm_kcalloc(&pdev->dev, in at91_pinctrl_probe_dt()
1318 info->ngroups, in at91_pinctrl_probe_dt()
1321 if (!info->groups) in at91_pinctrl_probe_dt()
1322 return -ENOMEM; in at91_pinctrl_probe_dt()
1324 dev_dbg(&pdev->dev, "nbanks = %d\n", gpio_banks); in at91_pinctrl_probe_dt()
1325 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1326 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1335 dev_err(&pdev->dev, "failed to parse function\n"); in at91_pinctrl_probe_dt()
1350 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in at91_pinctrl_probe()
1352 return -ENOMEM; in at91_pinctrl_probe()
1367 if (ngpio_chips_enabled < info->nactive_banks) { in at91_pinctrl_probe()
1368 dev_warn(&pdev->dev, in at91_pinctrl_probe()
1370 ngpio_chips_enabled, info->nactive_banks); in at91_pinctrl_probe()
1371 devm_kfree(&pdev->dev, info); in at91_pinctrl_probe()
1372 return -EPROBE_DEFER; in at91_pinctrl_probe()
1375 at91_pinctrl_desc.name = dev_name(&pdev->dev); in at91_pinctrl_probe()
1378 devm_kcalloc(&pdev->dev, in at91_pinctrl_probe()
1383 return -ENOMEM; in at91_pinctrl_probe()
1387 pdesc->number = k; in at91_pinctrl_probe()
1388 pdesc->name = kasprintf(GFP_KERNEL, "pio%c%d", i + 'A', j); in at91_pinctrl_probe()
1394 info->pctl = devm_pinctrl_register(&pdev->dev, &at91_pinctrl_desc, in at91_pinctrl_probe()
1397 if (IS_ERR(info->pctl)) { in at91_pinctrl_probe()
1398 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); in at91_pinctrl_probe()
1399 return PTR_ERR(info->pctl); in at91_pinctrl_probe()
1405 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); in at91_pinctrl_probe()
1407 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); in at91_pinctrl_probe()
1415 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get_direction()
1429 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_input()
1439 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get()
1451 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set()
1461 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set_multiple()
1463 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) in at91_gpio_set_multiple()
1465 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1466 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1476 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_output()
1491 void __iomem *pio = at91_gpio->regbase; in at91_gpio_dbg_show()
1497 mode = at91_gpio->ops->get_periph(pio, mask); in at91_gpio_dbg_show()
1499 gpio_label, chip->label, i); in at91_gpio_dbg_show()
1510 mode + 'A' - 1); in at91_gpio_dbg_show()
1521 * Then just request_irq() with the pin ID; it works like any ARM IRQ
1535 void __iomem *pio = at91_gpio->regbase; in gpio_irq_mask()
1536 unsigned mask = 1 << d->hwirq; in gpio_irq_mask()
1545 void __iomem *pio = at91_gpio->regbase; in gpio_irq_unmask()
1546 unsigned mask = 1 << d->hwirq; in gpio_irq_unmask()
1559 return -EINVAL; in gpio_irq_type()
1567 void __iomem *pio = at91_gpio->regbase; in alt_gpio_irq_type()
1568 unsigned mask = 1 << d->hwirq; in alt_gpio_irq_type()
1601 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); in alt_gpio_irq_type()
1602 return -EINVAL; in alt_gpio_irq_type()
1624 unsigned bank = at91_gpio->pioc_idx; in gpio_irq_set_wake()
1625 unsigned mask = 1 << d->hwirq; in gpio_irq_set_wake()
1628 return -EINVAL; in gpio_irq_set_wake()
1635 irq_set_irq_wake(at91_gpio->pioc_virq, state); in gpio_irq_set_wake()
1650 pio = gpio_chips[i]->regbase; in at91_pinctrl_gpio_suspend()
1657 clk_disable_unprepare(gpio_chips[i]->clock); in at91_pinctrl_gpio_suspend()
1659 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", in at91_pinctrl_gpio_suspend()
1674 pio = gpio_chips[i]->regbase; in at91_pinctrl_gpio_resume()
1677 clk_prepare_enable(gpio_chips[i]->clock); in at91_pinctrl_gpio_resume()
1693 void __iomem *pio = at91_gpio->regbase; in gpio_irq_handler()
1705 if (!at91_gpio->next) in gpio_irq_handler()
1707 at91_gpio = at91_gpio->next; in gpio_irq_handler()
1708 pio = at91_gpio->regbase; in gpio_irq_handler()
1709 gpio_chip = &at91_gpio->chip; in gpio_irq_handler()
1715 gpio_chip->irq.domain, n)); in gpio_irq_handler()
1719 /* now it may re-trigger */ in gpio_irq_handler()
1727 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1732 gpio_irqchip = devm_kzalloc(&pdev->dev, sizeof(*gpio_irqchip), in at91_gpio_of_irq_setup()
1735 return -ENOMEM; in at91_gpio_of_irq_setup()
1737 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); in at91_gpio_of_irq_setup()
1739 gpio_irqchip->name = "GPIO"; in at91_gpio_of_irq_setup()
1740 gpio_irqchip->irq_ack = gpio_irq_ack; in at91_gpio_of_irq_setup()
1741 gpio_irqchip->irq_disable = gpio_irq_mask; in at91_gpio_of_irq_setup()
1742 gpio_irqchip->irq_mask = gpio_irq_mask; in at91_gpio_of_irq_setup()
1743 gpio_irqchip->irq_unmask = gpio_irq_unmask; in at91_gpio_of_irq_setup()
1744 gpio_irqchip->irq_set_wake = gpio_irq_set_wake, in at91_gpio_of_irq_setup()
1745 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; in at91_gpio_of_irq_setup()
1748 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); in at91_gpio_of_irq_setup()
1755 girq = &at91_gpio->chip.irq; in at91_gpio_of_irq_setup()
1756 girq->chip = gpio_irqchip; in at91_gpio_of_irq_setup()
1757 girq->default_type = IRQ_TYPE_NONE; in at91_gpio_of_irq_setup()
1758 girq->handler = handle_edge_irq; in at91_gpio_of_irq_setup()
1765 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1767 girq->parent_handler = gpio_irq_handler; in at91_gpio_of_irq_setup()
1768 girq->num_parents = 1; in at91_gpio_of_irq_setup()
1769 girq->parents = devm_kcalloc(&pdev->dev, 1, in at91_gpio_of_irq_setup()
1770 sizeof(*girq->parents), in at91_gpio_of_irq_setup()
1772 if (!girq->parents) in at91_gpio_of_irq_setup()
1773 return -ENOMEM; in at91_gpio_of_irq_setup()
1774 girq->parents[0] = at91_gpio->pioc_virq; in at91_gpio_of_irq_setup()
1781 if (prev->next) { in at91_gpio_of_irq_setup()
1782 prev = prev->next; in at91_gpio_of_irq_setup()
1784 prev->next = at91_gpio; in at91_gpio_of_irq_setup()
1789 return -EINVAL; in at91_gpio_of_irq_setup()
1808 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1809 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1810 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1816 struct device_node *np = pdev->dev.of_node; in at91_gpio_probe()
1828 ret = -EBUSY; in at91_gpio_probe()
1838 at91_chip = devm_kzalloc(&pdev->dev, sizeof(*at91_chip), GFP_KERNEL); in at91_gpio_probe()
1840 ret = -ENOMEM; in at91_gpio_probe()
1844 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0); in at91_gpio_probe()
1845 if (IS_ERR(at91_chip->regbase)) { in at91_gpio_probe()
1846 ret = PTR_ERR(at91_chip->regbase); in at91_gpio_probe()
1850 at91_chip->ops = (struct at91_pinctrl_mux_ops *) in at91_gpio_probe()
1851 of_match_device(at91_gpio_of_match, &pdev->dev)->data; in at91_gpio_probe()
1852 at91_chip->pioc_virq = irq; in at91_gpio_probe()
1853 at91_chip->pioc_idx = alias_idx; in at91_gpio_probe()
1855 at91_chip->clock = devm_clk_get(&pdev->dev, NULL); in at91_gpio_probe()
1856 if (IS_ERR(at91_chip->clock)) { in at91_gpio_probe()
1857 dev_err(&pdev->dev, "failed to get clock, ignoring.\n"); in at91_gpio_probe()
1858 ret = PTR_ERR(at91_chip->clock); in at91_gpio_probe()
1862 ret = clk_prepare_enable(at91_chip->clock); in at91_gpio_probe()
1864 dev_err(&pdev->dev, "failed to prepare and enable clock, ignoring.\n"); in at91_gpio_probe()
1868 at91_chip->chip = at91_gpio_template; in at91_gpio_probe()
1870 chip = &at91_chip->chip; in at91_gpio_probe()
1871 chip->of_node = np; in at91_gpio_probe()
1872 chip->label = dev_name(&pdev->dev); in at91_gpio_probe()
1873 chip->parent = &pdev->dev; in at91_gpio_probe()
1874 chip->owner = THIS_MODULE; in at91_gpio_probe()
1875 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1877 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { in at91_gpio_probe()
1879 pr_err("at91_gpio.%d, gpio-nb >= %d failback to %d\n", in at91_gpio_probe()
1882 chip->ngpio = ngpio; in at91_gpio_probe()
1885 names = devm_kcalloc(&pdev->dev, chip->ngpio, sizeof(char *), in at91_gpio_probe()
1889 ret = -ENOMEM; in at91_gpio_probe()
1893 for (i = 0; i < chip->ngpio; i++) in at91_gpio_probe()
1894 names[i] = devm_kasprintf(&pdev->dev, GFP_KERNEL, "pio%c%d", alias_idx + 'A', i); in at91_gpio_probe()
1896 chip->names = (const char *const *)names; in at91_gpio_probe()
1898 range = &at91_chip->range; in at91_gpio_probe()
1899 range->name = chip->label; in at91_gpio_probe()
1900 range->id = alias_idx; in at91_gpio_probe()
1901 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1903 range->npins = chip->ngpio; in at91_gpio_probe()
1904 range->gc = chip; in at91_gpio_probe()
1917 dev_info(&pdev->dev, "at address %p\n", at91_chip->regbase); in at91_gpio_probe()
1923 clk_disable_unprepare(at91_chip->clock); in at91_gpio_probe()
1925 dev_err(&pdev->dev, "Failure %i for GPIO %i\n", ret, alias_idx); in at91_gpio_probe()
1932 .name = "gpio-at91",
1940 .name = "pinctrl-at91",