Lines Matching +full:conf +full:- +full:pd
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
26 #include <linux/pinctrl/pinconf-generic.h>
32 /* The Bank contains input-disable regisgers */
56 /* Raw value of Driver-Strength Bits */
63 /* Drive-Strength Intermediate Values */
64 #define DS_NULL -1
72 /* The Drive-Strength of 4WE Pad DS1 0 CO */
78 /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
96 /* The Drive-Strength of M31 Pad DS0 CO */
102 #define PD BIT(0) macro
113 #define PULL_UNKNOWN -1
115 /* Pull Options for 4WE Pad PUN PD CO */
117 #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
119 #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
122 /* Pull Options for 16ST Pad PUN PD CO */
124 #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
133 /* Pull Options for A/D Pad PUN PD CO */
135 #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
171 * struct atlas7_pad_conf - Atlas7 Pad Configuration
176 * @pupd_reg: The pull-up/down register offset.
177 * @drvstr_reg: The drive-strength register offset.
181 * @pupd_bit: The start bit of pull-up/down register.
182 * @drvstr_bit: The start bit of drive-strength register.
214 * struct atlas7_pad_status - Atlas7 Pad status
224 * struct atlas7_pad_mux - Atlas7 mux
228 * @dinput_reg: The Input-Disable register offset.
229 * @dinput_bit: The start bit of Input-Disable register.
230 * @dinput_val_reg: The Input-Disable-value register offset.
233 * @dinput_val_bit: The start bit of Input-Disable Value register.
263 * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
266 * from the driver-local pin enumeration space
324 #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
325 #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
326 #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
372 * refer to A7DA IO Summary - CS-314158-DD-4E.xls
548 PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
549 PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
550 PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
551 PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
552 PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
553 PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
554 PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
555 PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
556 PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
557 PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
558 PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
559 PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
560 PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
561 PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
562 PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
563 PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
564 PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
565 PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
567 PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
568 PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
569 PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
570 PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
571 PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
572 PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
573 PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
574 PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
575 PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
576 PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
577 PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
578 PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
579 PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
580 PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
581 PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
582 PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
583 PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
584 PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
585 PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
586 PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
587 PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
588 PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
589 PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
590 PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
591 PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
592 PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
593 PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
594 PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
595 PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
596 PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
597 PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
598 PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
599 PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
600 PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
601 PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
602 PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
603 PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
604 PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
605 PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
606 PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
607 PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
608 PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
609 PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
610 PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
611 PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
612 PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
613 PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
614 PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
615 PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
616 PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
617 PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
618 PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
619 PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
620 PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
621 PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
622 PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
623 PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
624 PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
625 PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
626 PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
627 PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
628 PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
629 PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
630 PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
631 PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
632 PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
633 PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
634 PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
635 PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
636 PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
637 PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
638 PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
639 PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
640 PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
641 PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
642 PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
643 PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
644 PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
645 PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
646 PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
647 PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
648 PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
649 PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
650 PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
651 PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
652 PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
653 PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
654 PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
655 PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
656 PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
657 PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
658 PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
659 PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
660 PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
661 PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
662 PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
663 PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
664 PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
665 PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
666 PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
667 PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
668 PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
669 PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
670 PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
671 PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
672 PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
673 PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
674 PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
675 PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
676 PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
677 PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
678 PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
679 PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
680 PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
681 PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
682 PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
683 PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
684 PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
685 PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
686 PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
687 PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
688 PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
689 PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
690 PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
691 PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
692 PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
693 PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
694 PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
695 PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
696 PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
697 PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
698 PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
699 PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
700 PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
701 PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
702 PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
703 PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
704 PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
705 PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
706 PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
707 PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
708 PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
709 PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
710 PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
711 PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
712 PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
4779 * struct atlas7_pull_info - Atlas7 Pad pull info
4802 { PD, PULL_UNKNOWN },
4814 { PD, PULL_UNKNOWN },
4825 { PULL_DISABLE, -1 },
4826 { PULL_ENABLE, -1 },
4831 { HIGH_HYSTERESIS, -1 },
4834 { PULL_DISABLE, -1 },
4835 { PULL_ENABLE, -1 },
4840 { HIGH_HYSTERESIS, -1 },
4841 { HIGH_Z, -1 },
4843 { PULL_DISABLE, -1 },
4844 { PULL_ENABLE, -1 },
4849 { HIGH_HYSTERESIS, -1 },
4852 { PULL_DISABLE, -1 },
4853 { PULL_ENABLE, -1 },
4868 * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
4903 * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
4936 return pmx->pctl_data->funcs_cnt; in atlas7_pmx_get_funcs_count()
4944 return pmx->pctl_data->funcs[selector].name; in atlas7_pmx_get_func_name()
4953 *groups = pmx->pctl_data->funcs[selector].groups; in atlas7_pmx_get_func_groups()
4954 *num_groups = pmx->pctl_data->funcs[selector].num_groups; in atlas7_pmx_get_func_groups()
4964 * All Input-Disable Control registers are located on IOCRTC. in __atlas7_pmx_pin_input_disable_set()
4968 if (mux->dinput_reg && mux->dinput_val_reg) { in __atlas7_pmx_pin_input_disable_set()
4969 writel(DI_MASK << mux->dinput_bit, in __atlas7_pmx_pin_input_disable_set()
4970 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); in __atlas7_pmx_pin_input_disable_set()
4971 writel(DI_DISABLE << mux->dinput_bit, in __atlas7_pmx_pin_input_disable_set()
4972 pmx->regs[BANK_DS] + mux->dinput_reg); in __atlas7_pmx_pin_input_disable_set()
4975 writel(DIV_MASK << mux->dinput_val_bit, in __atlas7_pmx_pin_input_disable_set()
4976 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); in __atlas7_pmx_pin_input_disable_set()
4977 writel(DIV_DISABLE << mux->dinput_val_bit, in __atlas7_pmx_pin_input_disable_set()
4978 pmx->regs[BANK_DS] + mux->dinput_val_reg); in __atlas7_pmx_pin_input_disable_set()
4986 if (mux->dinput_reg && mux->dinput_val_reg) { in __atlas7_pmx_pin_input_disable_clr()
4987 writel(DI_MASK << mux->dinput_bit, in __atlas7_pmx_pin_input_disable_clr()
4988 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg)); in __atlas7_pmx_pin_input_disable_clr()
4989 writel(DI_ENABLE << mux->dinput_bit, in __atlas7_pmx_pin_input_disable_clr()
4990 pmx->regs[BANK_DS] + mux->dinput_reg); in __atlas7_pmx_pin_input_disable_clr()
4992 writel(DIV_MASK << mux->dinput_val_bit, in __atlas7_pmx_pin_input_disable_clr()
4993 pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg)); in __atlas7_pmx_pin_input_disable_clr()
4994 writel(DIV_ENABLE << mux->dinput_val_bit, in __atlas7_pmx_pin_input_disable_clr()
4995 pmx->regs[BANK_DS] + mux->dinput_val_reg); in __atlas7_pmx_pin_input_disable_clr()
5000 struct atlas7_pad_config *conf, in __atlas7_pmx_pin_ad_sel() argument
5006 writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit, in __atlas7_pmx_pin_ad_sel()
5007 pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg)); in __atlas7_pmx_pin_ad_sel()
5010 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); in __atlas7_pmx_pin_ad_sel()
5011 regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit); in __atlas7_pmx_pin_ad_sel()
5012 writel(regv | (ad_sel << conf->ad_ctrl_bit), in __atlas7_pmx_pin_ad_sel()
5013 pmx->regs[bank] + conf->ad_ctrl_reg); in __atlas7_pmx_pin_ad_sel()
5015 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); in __atlas7_pmx_pin_ad_sel()
5017 bank, conf->ad_ctrl_reg, regv); in __atlas7_pmx_pin_ad_sel()
5022 struct atlas7_pad_config *conf, u32 bank) in __atlas7_pmx_pin_analog_enable() argument
5025 if (conf->type != PAD_T_AD) in __atlas7_pmx_pin_analog_enable()
5026 return -EINVAL; in __atlas7_pmx_pin_analog_enable()
5028 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0); in __atlas7_pmx_pin_analog_enable()
5032 struct atlas7_pad_config *conf, u32 bank) in __atlas7_pmx_pin_digital_enable() argument
5035 if (conf->type != PAD_T_AD) in __atlas7_pmx_pin_digital_enable()
5038 return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1); in __atlas7_pmx_pin_digital_enable()
5044 struct atlas7_pad_config *conf; in __atlas7_pmx_pin_enable() local
5053 conf = &pmx->pctl_data->confs[pin]; in __atlas7_pmx_pin_enable()
5058 ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank); in __atlas7_pmx_pin_enable()
5060 dev_err(pmx->dev, in __atlas7_pmx_pin_enable()
5067 ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank); in __atlas7_pmx_pin_enable()
5069 dev_err(pmx->dev, in __atlas7_pmx_pin_enable()
5076 writel(FUNC_CLEAR_MASK << conf->mux_bit, in __atlas7_pmx_pin_enable()
5077 pmx->regs[bank] + CLR_REG(conf->mux_reg)); in __atlas7_pmx_pin_enable()
5080 regv = readl(pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5081 regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit); in __atlas7_pmx_pin_enable()
5082 writel(regv | (func << conf->mux_bit), in __atlas7_pmx_pin_enable()
5083 pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5085 regv = readl(pmx->regs[bank] + conf->mux_reg); in __atlas7_pmx_pin_enable()
5087 bank, conf->mux_reg, regv); in __atlas7_pmx_pin_enable()
5102 pmx_func = &pmx->pctl_data->funcs[func_selector]; in atlas7_pmx_set_mux()
5103 pin_grp = &pmx->pctl_data->grps[group_selector]; in atlas7_pmx_set_mux()
5106 pmx_func->name, pin_grp->name); in atlas7_pmx_set_mux()
5109 if (pin_grp->pins == (unsigned int *)&sd3_9_pins) { in atlas7_pmx_set_mux()
5110 if (!strcmp(pmx_func->name, "sd9")) in atlas7_pmx_set_mux()
5111 writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL); in atlas7_pmx_set_mux()
5113 writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL); in atlas7_pmx_set_mux()
5116 grp_mux = pmx_func->grpmux; in atlas7_pmx_set_mux()
5118 for (idx = 0; idx < grp_mux->pad_mux_count; idx++) { in atlas7_pmx_set_mux()
5119 mux = &grp_mux->pad_mux_list[idx]; in atlas7_pmx_set_mux()
5121 ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func); in atlas7_pmx_set_mux()
5123 dev_err(pmx->dev, in atlas7_pmx_set_mux()
5125 pmx_func->name, pin_grp->name, in atlas7_pmx_set_mux()
5126 mux->pin, mux->func, ret); in atlas7_pmx_set_mux()
5132 pmx_func->name, pin_grp->name); in atlas7_pmx_set_mux()
5162 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; in altas7_pinctrl_set_pull_sel() local
5169 pull_info = &atlas7_pull_map[conf->type]; in altas7_pinctrl_set_pull_sel()
5170 pull_sel_reg = pmx->regs[bank] + conf->pupd_reg; in altas7_pinctrl_set_pull_sel()
5173 regv = pull_info->s2v[sel].data & pull_info->mask; in altas7_pinctrl_set_pull_sel()
5176 writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg)); in altas7_pinctrl_set_pull_sel()
5177 writel(regv << conf->pupd_bit, pull_sel_reg); in altas7_pinctrl_set_pull_sel()
5188 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; in __altas7_pinctrl_set_drive_strength_sel() local
5193 ds_info = &atlas7_ds_map[conf->type]; in __altas7_pinctrl_set_drive_strength_sel()
5194 if (sel & (~(ds_info->mask))) in __altas7_pinctrl_set_drive_strength_sel()
5198 ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg; in __altas7_pinctrl_set_drive_strength_sel()
5200 writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg)); in __altas7_pinctrl_set_drive_strength_sel()
5201 writel(sel << conf->drvstr_bit, ds_sel_reg); in __altas7_pinctrl_set_drive_strength_sel()
5207 pin, conf->type, sel); in __altas7_pinctrl_set_drive_strength_sel()
5208 return -ENOTSUPP; in __altas7_pinctrl_set_drive_strength_sel()
5215 struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin]; in altas7_pinctrl_set_drive_strength_sel() local
5216 u32 type = conf->type; in altas7_pinctrl_set_drive_strength_sel()
5220 sel = convert_current_to_drive_strength(conf->type, ma); in altas7_pinctrl_set_drive_strength_sel()
5224 return -ENOTSUPP; in altas7_pinctrl_set_drive_strength_sel()
5240 dev_dbg(pmx->dev, in atlas7_pmx_gpio_request_enable()
5242 for (idx = 0; idx < range->npins; idx++) { in atlas7_pmx_gpio_request_enable()
5243 if (pin == range->pins[idx]) in atlas7_pmx_gpio_request_enable()
5247 if (idx >= range->npins) { in atlas7_pmx_gpio_request_enable()
5248 dev_err(pmx->dev, in atlas7_pmx_gpio_request_enable()
5251 return -EPERM; in atlas7_pmx_gpio_request_enable()
5271 return pmx->pctl_data->grps_cnt; in atlas7_pinctrl_get_groups_count()
5279 return pmx->pctl_data->grps[group].name; in atlas7_pinctrl_get_group_name()
5287 *num_pins = pmx->pctl_data->grps[group].num_pins; in atlas7_pinctrl_get_group_pins()
5288 *pins = pmx->pctl_data->grps[group].pins; in atlas7_pinctrl_get_group_pins()
5365 return -ENOTSUPP; in atlas7_pin_config_set()
5388 return -ENOTSUPP; in atlas7_pin_config_group_set()
5403 struct device_node *np = pdev->dev.of_node; in atlas7_pinmux_probe()
5409 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); in atlas7_pinmux_probe()
5411 return -ENOMEM; in atlas7_pinmux_probe()
5418 return -EINVAL; in atlas7_pinmux_probe()
5425 pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res); in atlas7_pinmux_probe()
5426 if (IS_ERR(pmx->sys2pci_base)) in atlas7_pinmux_probe()
5427 return -ENOMEM; in atlas7_pinmux_probe()
5429 pmx->dev = &pdev->dev; in atlas7_pinmux_probe()
5431 pmx->pctl_data = &atlas7_ioc_data; in atlas7_pinmux_probe()
5432 pmx->pctl_desc.name = "pinctrl-atlas7"; in atlas7_pinmux_probe()
5433 pmx->pctl_desc.pins = pmx->pctl_data->pads; in atlas7_pinmux_probe()
5434 pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt; in atlas7_pinmux_probe()
5435 pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops; in atlas7_pinmux_probe()
5436 pmx->pctl_desc.pmxops = &atlas7_pinmux_ops; in atlas7_pinmux_probe()
5437 pmx->pctl_desc.confops = &atlas7_pinconf_ops; in atlas7_pinmux_probe()
5440 pmx->regs[idx] = of_iomap(np, idx); in atlas7_pinmux_probe()
5441 if (!pmx->regs[idx]) { in atlas7_pinmux_probe()
5442 dev_err(&pdev->dev, in atlas7_pinmux_probe()
5444 ret = -ENOMEM; in atlas7_pinmux_probe()
5450 pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx); in atlas7_pinmux_probe()
5451 if (IS_ERR(pmx->pctl)) { in atlas7_pinmux_probe()
5452 dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n"); in atlas7_pinmux_probe()
5453 ret = PTR_ERR(pmx->pctl); in atlas7_pinmux_probe()
5459 dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n"); in atlas7_pinmux_probe()
5465 if (!pmx->regs[idx]) in atlas7_pinmux_probe()
5467 iounmap(pmx->regs[idx]); in atlas7_pinmux_probe()
5478 struct atlas7_pad_config *conf; in atlas7_pinmux_suspend_noirq() local
5485 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) { in atlas7_pinmux_suspend_noirq()
5487 conf = &pmx->pctl_data->confs[idx]; in atlas7_pinmux_suspend_noirq()
5489 status = &pmx->sleep_data[idx]; in atlas7_pinmux_suspend_noirq()
5492 regv = readl(pmx->regs[bank] + conf->mux_reg); in atlas7_pinmux_suspend_noirq()
5493 status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK; in atlas7_pinmux_suspend_noirq()
5496 if (conf->ad_ctrl_reg == -1) in atlas7_pinmux_suspend_noirq()
5499 regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg); in atlas7_pinmux_suspend_noirq()
5500 if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK))) in atlas7_pinmux_suspend_noirq()
5501 status->func = FUNC_ANALOGUE; in atlas7_pinmux_suspend_noirq()
5504 if (conf->drvstr_reg == -1) in atlas7_pinmux_suspend_noirq()
5508 ds_info = &atlas7_ds_map[conf->type]; in atlas7_pinmux_suspend_noirq()
5509 regv = readl(pmx->regs[bank] + conf->drvstr_reg); in atlas7_pinmux_suspend_noirq()
5510 status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask; in atlas7_pinmux_suspend_noirq()
5514 pull_info = &atlas7_pull_map[conf->type]; in atlas7_pinmux_suspend_noirq()
5515 regv = readl(pmx->regs[bank] + conf->pupd_reg); in atlas7_pinmux_suspend_noirq()
5516 regv = (regv >> conf->pupd_bit) & pull_info->mask; in atlas7_pinmux_suspend_noirq()
5517 status->pull = pull_info->v2s[regv].data; in atlas7_pinmux_suspend_noirq()
5525 pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] + in atlas7_pinmux_suspend_noirq()
5527 pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] + in atlas7_pinmux_suspend_noirq()
5540 for (idx = 0; idx < pmx->pctl_desc.npins; idx++) { in atlas7_pinmux_resume_noirq()
5542 status = &pmx->sleep_data[idx]; in atlas7_pinmux_resume_noirq()
5545 __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff); in atlas7_pinmux_resume_noirq()
5547 if (FUNC_ANALOGUE == status->func) in atlas7_pinmux_resume_noirq()
5551 __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx, in atlas7_pinmux_resume_noirq()
5552 (u32)status->dstr & 0xff); in atlas7_pinmux_resume_noirq()
5556 altas7_pinctrl_set_pull_sel(pmx->pctl, idx, in atlas7_pinmux_resume_noirq()
5557 (u32)status->pull & 0xff); in atlas7_pinmux_resume_noirq()
5565 writel(~0, pmx->regs[BANK_DS] + in atlas7_pinmux_resume_noirq()
5567 writel(pmx->status_ds[idx], pmx->regs[BANK_DS] + in atlas7_pinmux_resume_noirq()
5569 writel(~0, pmx->regs[BANK_DS] + in atlas7_pinmux_resume_noirq()
5571 writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] + in atlas7_pinmux_resume_noirq()
5587 { .compatible = "sirf,atlas7-ioc",},
5593 .name = "atlas7-ioc",
5615 return &a7gc->banks[GPIO_TO_BANK(gpio)]; in atlas7_gpio_to_bank()
5624 ofs = gpio - bank->gpio_offset; in __atlas7_gpio_to_pin()
5625 if (ofs >= bank->ngpio) in __atlas7_gpio_to_pin()
5626 return -ENODEV; in __atlas7_gpio_to_pin()
5628 return bank->gpio_pins[ofs]; in __atlas7_gpio_to_pin()
5640 bank = atlas7_gpio_to_bank(a7gc, d->hwirq); in atlas7_gpio_irq_ack()
5641 pin_in_bank = d->hwirq - bank->gpio_offset; in atlas7_gpio_irq_ack()
5644 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_irq_ack()
5650 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_irq_ack()
5660 pin_in_bank = idx - bank->gpio_offset; in __atlas7_gpio_irq_mask()
5675 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_irq_mask()
5677 __atlas7_gpio_irq_mask(a7gc, d->hwirq); in atlas7_gpio_irq_mask()
5679 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_irq_mask()
5691 bank = atlas7_gpio_to_bank(a7gc, d->hwirq); in atlas7_gpio_irq_unmask()
5692 pin_in_bank = d->hwirq - bank->gpio_offset; in atlas7_gpio_irq_unmask()
5695 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_irq_unmask()
5702 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_irq_unmask()
5715 bank = atlas7_gpio_to_bank(a7gc, d->hwirq); in atlas7_gpio_irq_type()
5716 pin_in_bank = d->hwirq - bank->gpio_offset; in atlas7_gpio_irq_type()
5719 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_irq_type()
5762 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_irq_type()
5768 .name = "atlas7-gpio-irq",
5785 for (idx = 0; idx < a7gc->nbank; idx++) { in atlas7_gpio_handle_irq()
5786 bank = &a7gc->banks[idx]; in atlas7_gpio_handle_irq()
5787 if (bank->irq == irq) in atlas7_gpio_handle_irq()
5790 BUG_ON(idx == a7gc->nbank); in atlas7_gpio_handle_irq()
5797 __func__, gc->label, status); in atlas7_gpio_handle_irq()
5811 __func__, gc->label, in atlas7_gpio_handle_irq()
5812 bank->gpio_offset + pin_in_bank); in atlas7_gpio_handle_irq()
5814 irq_find_mapping(gc->irq.domain, in atlas7_gpio_handle_irq()
5815 bank->gpio_offset + pin_in_bank)); in atlas7_gpio_handle_irq()
5818 if (++pin_in_bank >= bank->ngpio) in atlas7_gpio_handle_irq()
5835 pin_in_bank = gpio - bank->gpio_offset; in __atlas7_gpio_set_input()
5854 if (pinctrl_gpio_request(chip->base + gpio)) in atlas7_gpio_request()
5855 return -ENODEV; in atlas7_gpio_request()
5857 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_request()
5866 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_request()
5877 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_free()
5882 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_free()
5884 pinctrl_gpio_free(chip->base + gpio); in atlas7_gpio_free()
5893 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_direction_input()
5897 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_direction_input()
5910 pin_in_bank = gpio - bank->gpio_offset; in __atlas7_gpio_set_output()
5930 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_direction_output()
5934 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_direction_output()
5948 pin_in_bank = gpio - bank->gpio_offset; in atlas7_gpio_get_value()
5950 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_get_value()
5954 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_get_value()
5969 pin_in_bank = gpio - bank->gpio_offset; in atlas7_gpio_set_value()
5972 raw_spin_lock_irqsave(&a7gc->lock, flags); in atlas7_gpio_set_value()
5981 raw_spin_unlock_irqrestore(&a7gc->lock, flags); in atlas7_gpio_set_value()
5985 { .compatible = "sirf,atlas7-gpio", },
5991 struct device_node *np = pdev->dev.of_node; in atlas7_gpio_probe()
5998 ret = of_property_read_u32(np, "gpio-banks", &nbank); in atlas7_gpio_probe()
6000 dev_err(&pdev->dev, in atlas7_gpio_probe()
6007 a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank), in atlas7_gpio_probe()
6010 return -ENOMEM; in atlas7_gpio_probe()
6013 a7gc->clk = of_clk_get(np, 0); in atlas7_gpio_probe()
6014 if (!IS_ERR(a7gc->clk)) { in atlas7_gpio_probe()
6015 ret = clk_prepare_enable(a7gc->clk); in atlas7_gpio_probe()
6017 dev_err(&pdev->dev, in atlas7_gpio_probe()
6024 a7gc->reg = of_iomap(np, 0); in atlas7_gpio_probe()
6025 if (!a7gc->reg) { in atlas7_gpio_probe()
6026 dev_err(&pdev->dev, "Could not map GPIO Registers!\n"); in atlas7_gpio_probe()
6027 return -ENOMEM; in atlas7_gpio_probe()
6030 a7gc->nbank = nbank; in atlas7_gpio_probe()
6031 raw_spin_lock_init(&a7gc->lock); in atlas7_gpio_probe()
6034 chip = &a7gc->chip; in atlas7_gpio_probe()
6035 chip->request = atlas7_gpio_request; in atlas7_gpio_probe()
6036 chip->free = atlas7_gpio_free; in atlas7_gpio_probe()
6037 chip->direction_input = atlas7_gpio_direction_input; in atlas7_gpio_probe()
6038 chip->get = atlas7_gpio_get_value; in atlas7_gpio_probe()
6039 chip->direction_output = atlas7_gpio_direction_output; in atlas7_gpio_probe()
6040 chip->set = atlas7_gpio_set_value; in atlas7_gpio_probe()
6041 chip->base = -1; in atlas7_gpio_probe()
6043 chip->ngpio = NGPIO_OF_BANK * nbank; in atlas7_gpio_probe()
6044 chip->label = kstrdup(np->name, GFP_KERNEL); in atlas7_gpio_probe()
6045 chip->of_node = np; in atlas7_gpio_probe()
6046 chip->of_gpio_n_cells = 2; in atlas7_gpio_probe()
6047 chip->parent = &pdev->dev; in atlas7_gpio_probe()
6049 girq = &chip->irq; in atlas7_gpio_probe()
6050 girq->chip = &atlas7_gpio_irq_chip; in atlas7_gpio_probe()
6051 girq->parent_handler = atlas7_gpio_handle_irq; in atlas7_gpio_probe()
6052 girq->num_parents = nbank; in atlas7_gpio_probe()
6053 girq->parents = devm_kcalloc(&pdev->dev, nbank, in atlas7_gpio_probe()
6054 sizeof(*girq->parents), in atlas7_gpio_probe()
6056 if (!girq->parents) in atlas7_gpio_probe()
6057 return -ENOMEM; in atlas7_gpio_probe()
6061 bank = &a7gc->banks[idx]; in atlas7_gpio_probe()
6063 bank->base = ATLAS7_GPIO_BASE(a7gc, idx); in atlas7_gpio_probe()
6064 bank->gpio_offset = idx * NGPIO_OF_BANK; in atlas7_gpio_probe()
6069 dev_err(&pdev->dev, in atlas7_gpio_probe()
6072 ret = -ENXIO; in atlas7_gpio_probe()
6075 bank->irq = ret; in atlas7_gpio_probe()
6076 girq->parents[idx] = ret; in atlas7_gpio_probe()
6078 girq->default_type = IRQ_TYPE_NONE; in atlas7_gpio_probe()
6079 girq->handler = handle_level_irq; in atlas7_gpio_probe()
6084 dev_err(&pdev->dev, in atlas7_gpio_probe()
6091 dev_info(&pdev->dev, "add to system.\n"); in atlas7_gpio_probe()
6105 for (idx = 0; idx < a7gc->nbank; idx++) { in atlas7_gpio_suspend_noirq()
6106 bank = &a7gc->banks[idx]; in atlas7_gpio_suspend_noirq()
6107 for (pin = 0; pin < bank->ngpio; pin++) { in atlas7_gpio_suspend_noirq()
6109 bank->sleep_data[pin] = readl(ctrl_reg); in atlas7_gpio_suspend_noirq()
6123 for (idx = 0; idx < a7gc->nbank; idx++) { in atlas7_gpio_resume_noirq()
6124 bank = &a7gc->banks[idx]; in atlas7_gpio_resume_noirq()
6125 for (pin = 0; pin < bank->ngpio; pin++) { in atlas7_gpio_resume_noirq()
6127 writel(bank->sleep_data[pin], ctrl_reg); in atlas7_gpio_resume_noirq()
6144 .name = "atlas7-gpio",