Lines Matching +full:pctl +full:- +full:regmap
1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/regmap.h>
33 #include "../pinctrl-utils.h"
34 #include "pinctrl-stm32.h"
110 struct regmap *regmap; member
145 return function - 1; in stm32_gpio_get_alt()
156 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
157 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
163 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
165 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
166 bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT; in stm32_gpio_backup_mode()
172 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE); in stm32_gpio_backup_driving()
173 bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE; in stm32_gpio_backup_driving()
179 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK; in stm32_gpio_backup_speed()
180 bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT; in stm32_gpio_backup_speed()
186 bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK; in stm32_gpio_backup_bias()
187 bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT; in stm32_gpio_backup_bias()
200 clk_enable(bank->clk); in __stm32_gpio_set()
202 writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); in __stm32_gpio_set()
204 clk_disable(bank->clk); in __stm32_gpio_set()
210 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_request() local
212 int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); in stm32_gpio_request()
214 range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); in stm32_gpio_request()
216 dev_err(pctl->dev, "pin %d not in range.\n", pin); in stm32_gpio_request()
217 return -EINVAL; in stm32_gpio_request()
220 return pinctrl_gpio_request(chip->base + offset); in stm32_gpio_request()
225 pinctrl_gpio_free(chip->base + offset); in stm32_gpio_free()
232 return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); in stm32_gpio_get_noclk()
240 clk_enable(bank->clk); in stm32_gpio_get()
244 clk_disable(bank->clk); in stm32_gpio_get()
258 return pinctrl_gpio_direction_input(chip->base + offset); in stm32_gpio_direction_input()
267 pinctrl_gpio_direction_output(chip->base + offset); in stm32_gpio_direction_output()
278 fwspec.fwnode = bank->fwnode; in stm32_gpio_to_irq()
299 ret = -EINVAL; in stm32_gpio_get_direction()
318 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_irq_trigger()
322 if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK)) in stm32_gpio_irq_trigger()
326 level = stm32_gpio_get_noclk(&bank->gpio_chip, d->hwirq); in stm32_gpio_irq_trigger()
327 if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) || in stm32_gpio_irq_trigger()
328 (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH)) in stm32_gpio_irq_trigger()
340 struct stm32_gpio_bank *bank = d->domain->host_data; in stm32_gpio_set_type()
356 return -EINVAL; in stm32_gpio_set_type()
359 bank->irq_type[d->hwirq] = type; in stm32_gpio_set_type()
366 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_request_resources()
367 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_irq_request_resources() local
371 ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
375 ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_request_resources()
377 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", in stm32_gpio_irq_request_resources()
378 irq_data->hwirq); in stm32_gpio_irq_request_resources()
384 clk_enable(bank->clk); in stm32_gpio_irq_request_resources()
391 struct stm32_gpio_bank *bank = irq_data->domain->host_data; in stm32_gpio_irq_release_resources()
393 if (bank->irq_type[irq_data->hwirq] & IRQ_TYPE_LEVEL_MASK) in stm32_gpio_irq_release_resources()
394 clk_disable(bank->clk); in stm32_gpio_irq_release_resources()
396 gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); in stm32_gpio_irq_release_resources()
422 if ((fwspec->param_count != 2) || in stm32_gpio_domain_translate()
423 (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) in stm32_gpio_domain_translate()
424 return -EINVAL; in stm32_gpio_domain_translate()
426 *hwirq = fwspec->param[0]; in stm32_gpio_domain_translate()
427 *type = fwspec->param[1]; in stm32_gpio_domain_translate()
434 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_activate()
435 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_activate() local
443 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_activate()
445 if (pctl->hwlock) { in stm32_gpio_domain_activate()
446 ret = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_gpio_domain_activate()
449 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_gpio_domain_activate()
454 if (pctl->irqmux_map & BIT(irq_data->hwirq)) { in stm32_gpio_domain_activate()
455 dev_err(pctl->dev, "irq line %ld already requested.\n", in stm32_gpio_domain_activate()
456 irq_data->hwirq); in stm32_gpio_domain_activate()
457 ret = -EBUSY; in stm32_gpio_domain_activate()
458 if (pctl->hwlock) in stm32_gpio_domain_activate()
459 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
462 pctl->irqmux_map |= BIT(irq_data->hwirq); in stm32_gpio_domain_activate()
465 regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr); in stm32_gpio_domain_activate()
467 if (pctl->hwlock) in stm32_gpio_domain_activate()
468 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_gpio_domain_activate()
471 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_activate()
478 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_deactivate()
479 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_gpio_domain_deactivate() local
482 spin_lock_irqsave(&pctl->irqmux_lock, flags); in stm32_gpio_domain_deactivate()
483 pctl->irqmux_map &= ~BIT(irq_data->hwirq); in stm32_gpio_domain_deactivate()
484 spin_unlock_irqrestore(&pctl->irqmux_lock, flags); in stm32_gpio_domain_deactivate()
491 struct stm32_gpio_bank *bank = d->host_data; in stm32_gpio_domain_alloc()
496 hwirq = fwspec->param[0]; in stm32_gpio_domain_alloc()
497 parent_fwspec.fwnode = d->parent->fwnode; in stm32_gpio_domain_alloc()
499 parent_fwspec.param[0] = fwspec->param[0]; in stm32_gpio_domain_alloc()
500 parent_fwspec.param[1] = fwspec->param[1]; in stm32_gpio_domain_alloc()
518 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) in stm32_pctrl_find_group_by_pin() argument
522 for (i = 0; i < pctl->ngroups; i++) { in stm32_pctrl_find_group_by_pin()
523 struct stm32_pinctrl_group *grp = pctl->groups + i; in stm32_pctrl_find_group_by_pin()
525 if (grp->pin == pin) in stm32_pctrl_find_group_by_pin()
532 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, in stm32_pctrl_is_function_valid() argument
537 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_is_function_valid()
538 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_is_function_valid()
539 const struct stm32_desc_function *func = pin->functions; in stm32_pctrl_is_function_valid()
541 if (pin->pin.number != pin_num) in stm32_pctrl_is_function_valid()
544 while (func && func->name) { in stm32_pctrl_is_function_valid()
545 if (func->num == fnum) in stm32_pctrl_is_function_valid()
556 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, in stm32_pctrl_dt_node_to_map_func() argument
562 return -ENOSPC; in stm32_pctrl_dt_node_to_map_func()
565 (*map)[*num_maps].data.mux.group = grp->name; in stm32_pctrl_dt_node_to_map_func()
567 if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { in stm32_pctrl_dt_node_to_map_func()
568 dev_err(pctl->dev, "invalid function %d on pin %d .\n", in stm32_pctrl_dt_node_to_map_func()
570 return -EINVAL; in stm32_pctrl_dt_node_to_map_func()
585 struct stm32_pinctrl *pctl; in stm32_pctrl_dt_subnode_to_map() local
595 pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_dt_subnode_to_map()
599 dev_err(pctl->dev, "missing pins property in node %pOFn .\n", in stm32_pctrl_dt_subnode_to_map()
601 return -EINVAL; in stm32_pctrl_dt_subnode_to_map()
612 num_pins = pins->length / sizeof(u32); in stm32_pctrl_dt_subnode_to_map()
621 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
641 if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { in stm32_pctrl_dt_subnode_to_map()
642 dev_err(pctl->dev, "invalid function.\n"); in stm32_pctrl_dt_subnode_to_map()
643 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
647 grp = stm32_pctrl_find_group_by_pin(pctl, pin); in stm32_pctrl_dt_subnode_to_map()
649 dev_err(pctl->dev, "unable to match pin %d to group\n", in stm32_pctrl_dt_subnode_to_map()
651 err = -EINVAL; in stm32_pctrl_dt_subnode_to_map()
655 err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, in stm32_pctrl_dt_subnode_to_map()
662 reserved_maps, num_maps, grp->name, in stm32_pctrl_dt_subnode_to_map()
702 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_groups_count() local
704 return pctl->ngroups; in stm32_pctrl_get_groups_count()
710 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_name() local
712 return pctl->groups[group].name; in stm32_pctrl_get_group_name()
720 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pctrl_get_group_pins() local
722 *pins = (unsigned *)&pctl->groups[group].pin; in stm32_pctrl_get_group_pins()
755 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_get_func_groups() local
757 *groups = pctl->grp_names; in stm32_pmx_get_func_groups()
758 *num_groups = pctl->ngroups; in stm32_pmx_get_func_groups()
766 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pmx_set_mode() local
773 clk_enable(bank->clk); in stm32_pmx_set_mode()
774 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_set_mode()
776 if (pctl->hwlock) { in stm32_pmx_set_mode()
777 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pmx_set_mode()
780 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pmx_set_mode()
785 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_set_mode()
788 writel_relaxed(val, bank->base + alt_offset); in stm32_pmx_set_mode()
790 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
793 writel_relaxed(val, bank->base + STM32_GPIO_MODER); in stm32_pmx_set_mode()
795 if (pctl->hwlock) in stm32_pmx_set_mode()
796 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pmx_set_mode()
801 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_set_mode()
802 clk_disable(bank->clk); in stm32_pmx_set_mode()
815 clk_enable(bank->clk); in stm32_pmx_get_mode()
816 spin_lock_irqsave(&bank->lock, flags); in stm32_pmx_get_mode()
818 val = readl_relaxed(bank->base + alt_offset); in stm32_pmx_get_mode()
822 val = readl_relaxed(bank->base + STM32_GPIO_MODER); in stm32_pmx_get_mode()
826 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pmx_get_mode()
827 clk_disable(bank->clk); in stm32_pmx_get_mode()
835 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pmx_set_mux() local
836 struct stm32_pinctrl_group *g = pctl->groups + group; in stm32_pmx_set_mux()
842 ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); in stm32_pmx_set_mux()
844 dev_err(pctl->dev, "invalid function %d on group %d .\n", in stm32_pmx_set_mux()
846 return -EINVAL; in stm32_pmx_set_mux()
849 range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); in stm32_pmx_set_mux()
851 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pmx_set_mux()
852 return -EINVAL; in stm32_pmx_set_mux()
855 bank = gpiochip_get_data(range->gc); in stm32_pmx_set_mux()
856 pin = stm32_gpio_pin(g->pin); in stm32_pmx_set_mux()
868 struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); in stm32_pmx_gpio_set_direction()
888 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_driving() local
893 clk_enable(bank->clk); in stm32_pconf_set_driving()
894 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_driving()
896 if (pctl->hwlock) { in stm32_pconf_set_driving()
897 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_driving()
900 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_driving()
905 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
908 writel_relaxed(val, bank->base + STM32_GPIO_TYPER); in stm32_pconf_set_driving()
910 if (pctl->hwlock) in stm32_pconf_set_driving()
911 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_driving()
916 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_driving()
917 clk_disable(bank->clk); in stm32_pconf_set_driving()
928 clk_enable(bank->clk); in stm32_pconf_get_driving()
929 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_driving()
931 val = readl_relaxed(bank->base + STM32_GPIO_TYPER); in stm32_pconf_get_driving()
934 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_driving()
935 clk_disable(bank->clk); in stm32_pconf_get_driving()
943 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_speed() local
948 clk_enable(bank->clk); in stm32_pconf_set_speed()
949 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_speed()
951 if (pctl->hwlock) { in stm32_pconf_set_speed()
952 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_speed()
955 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_speed()
960 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
963 writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_set_speed()
965 if (pctl->hwlock) in stm32_pconf_set_speed()
966 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_speed()
971 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_speed()
972 clk_disable(bank->clk); in stm32_pconf_set_speed()
983 clk_enable(bank->clk); in stm32_pconf_get_speed()
984 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_speed()
986 val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); in stm32_pconf_get_speed()
989 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_speed()
990 clk_disable(bank->clk); in stm32_pconf_get_speed()
998 struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); in stm32_pconf_set_bias() local
1003 clk_enable(bank->clk); in stm32_pconf_set_bias()
1004 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_set_bias()
1006 if (pctl->hwlock) { in stm32_pconf_set_bias()
1007 err = hwspin_lock_timeout_in_atomic(pctl->hwlock, in stm32_pconf_set_bias()
1010 dev_err(pctl->dev, "Can't get hwspinlock\n"); in stm32_pconf_set_bias()
1015 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1018 writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); in stm32_pconf_set_bias()
1020 if (pctl->hwlock) in stm32_pconf_set_bias()
1021 hwspin_unlock_in_atomic(pctl->hwlock); in stm32_pconf_set_bias()
1026 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_set_bias()
1027 clk_disable(bank->clk); in stm32_pconf_set_bias()
1038 clk_enable(bank->clk); in stm32_pconf_get_bias()
1039 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get_bias()
1041 val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); in stm32_pconf_get_bias()
1044 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get_bias()
1045 clk_disable(bank->clk); in stm32_pconf_get_bias()
1056 clk_enable(bank->clk); in stm32_pconf_get()
1057 spin_lock_irqsave(&bank->lock, flags); in stm32_pconf_get()
1060 val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & in stm32_pconf_get()
1063 val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & in stm32_pconf_get()
1066 spin_unlock_irqrestore(&bank->lock, flags); in stm32_pconf_get()
1067 clk_disable(bank->clk); in stm32_pconf_get()
1076 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_parse_conf() local
1083 dev_err(pctl->dev, "No gpio range defined.\n"); in stm32_pconf_parse_conf()
1084 return -EINVAL; in stm32_pconf_parse_conf()
1087 bank = gpiochip_get_data(range->gc); in stm32_pconf_parse_conf()
1114 ret = -ENOTSUPP; in stm32_pconf_parse_conf()
1124 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_get() local
1126 *config = pctl->groups[group].config; in stm32_pconf_group_get()
1134 struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); in stm32_pconf_group_set() local
1135 struct stm32_pinctrl_group *g = &pctl->groups[group]; in stm32_pconf_group_set()
1139 mutex_lock(&pctldev->mutex); in stm32_pconf_group_set()
1140 ret = stm32_pconf_parse_conf(pctldev, g->pin, in stm32_pconf_group_set()
1143 mutex_unlock(&pctldev->mutex); in stm32_pconf_group_set()
1147 g->config = configs[i]; in stm32_pconf_group_set()
1189 bank = gpiochip_get_data(range->gc); in stm32_pconf_dbg_show()
1201 seq_printf(s, "- %s - %s", in stm32_pconf_dbg_show()
1211 seq_printf(s, "- %s - %s - %s - %s %s", in stm32_pconf_dbg_show()
1222 seq_printf(s, "%d - %s - %s - %s %s", alt, in stm32_pconf_dbg_show()
1241 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, in stm32_gpiolib_register_bank() argument
1244 struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; in stm32_gpiolib_register_bank()
1246 struct pinctrl_gpio_range *range = &bank->range; in stm32_gpiolib_register_bank()
1248 struct device *dev = pctl->dev; in stm32_gpiolib_register_bank()
1253 if (!IS_ERR(bank->rstc)) in stm32_gpiolib_register_bank()
1254 reset_control_deassert(bank->rstc); in stm32_gpiolib_register_bank()
1257 return -ENODEV; in stm32_gpiolib_register_bank()
1259 bank->base = devm_ioremap_resource(dev, &res); in stm32_gpiolib_register_bank()
1260 if (IS_ERR(bank->base)) in stm32_gpiolib_register_bank()
1261 return PTR_ERR(bank->base); in stm32_gpiolib_register_bank()
1263 err = clk_prepare(bank->clk); in stm32_gpiolib_register_bank()
1269 bank->gpio_chip = stm32_gpio_template; in stm32_gpiolib_register_bank()
1271 of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1273 if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, i, &args)) { in stm32_gpiolib_register_bank()
1275 bank->gpio_chip.base = args.args[1]; in stm32_gpiolib_register_bank()
1279 while (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, ++i, &args)) in stm32_gpiolib_register_bank()
1282 bank_nr = pctl->nbanks; in stm32_gpiolib_register_bank()
1283 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1284 range->name = bank->gpio_chip.label; in stm32_gpiolib_register_bank()
1285 range->id = bank_nr; in stm32_gpiolib_register_bank()
1286 range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1287 range->base = range->id * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1288 range->npins = npins; in stm32_gpiolib_register_bank()
1289 range->gc = &bank->gpio_chip; in stm32_gpiolib_register_bank()
1290 pinctrl_add_gpio_range(pctl->pctl_dev, in stm32_gpiolib_register_bank()
1291 &pctl->banks[bank_nr].range); in stm32_gpiolib_register_bank()
1294 if (of_property_read_u32(np, "st,bank-ioport", &bank_ioport_nr)) in stm32_gpiolib_register_bank()
1297 bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; in stm32_gpiolib_register_bank()
1299 bank->gpio_chip.ngpio = npins; in stm32_gpiolib_register_bank()
1300 bank->gpio_chip.of_node = np; in stm32_gpiolib_register_bank()
1301 bank->gpio_chip.parent = dev; in stm32_gpiolib_register_bank()
1302 bank->bank_nr = bank_nr; in stm32_gpiolib_register_bank()
1303 bank->bank_ioport_nr = bank_ioport_nr; in stm32_gpiolib_register_bank()
1304 spin_lock_init(&bank->lock); in stm32_gpiolib_register_bank()
1306 if (pctl->domain) { in stm32_gpiolib_register_bank()
1308 bank->fwnode = of_node_to_fwnode(np); in stm32_gpiolib_register_bank()
1310 bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE, in stm32_gpiolib_register_bank()
1311 bank->fwnode, &stm32_gpio_domain_ops, in stm32_gpiolib_register_bank()
1314 if (!bank->domain) in stm32_gpiolib_register_bank()
1315 return -ENODEV; in stm32_gpiolib_register_bank()
1318 err = gpiochip_add_data(&bank->gpio_chip, bank); in stm32_gpiolib_register_bank()
1324 dev_info(dev, "%s bank added\n", bank->gpio_chip.label); in stm32_gpiolib_register_bank()
1333 if (!of_find_property(np, "interrupt-parent", NULL)) in stm32_pctrl_get_irq_domain()
1338 return ERR_PTR(-ENXIO); in stm32_pctrl_get_irq_domain()
1344 return ERR_PTR(-EPROBE_DEFER); in stm32_pctrl_get_irq_domain()
1350 struct stm32_pinctrl *pctl) in stm32_pctrl_dt_setup_irq() argument
1352 struct device_node *np = pdev->dev.of_node; in stm32_pctrl_dt_setup_irq()
1353 struct device *dev = &pdev->dev; in stm32_pctrl_dt_setup_irq()
1354 struct regmap *rm; in stm32_pctrl_dt_setup_irq()
1358 pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); in stm32_pctrl_dt_setup_irq()
1359 if (IS_ERR(pctl->regmap)) in stm32_pctrl_dt_setup_irq()
1360 return PTR_ERR(pctl->regmap); in stm32_pctrl_dt_setup_irq()
1362 rm = pctl->regmap; in stm32_pctrl_dt_setup_irq()
1379 mux.msb = mux.lsb + mask_width - 1; in stm32_pctrl_dt_setup_irq()
1384 pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); in stm32_pctrl_dt_setup_irq()
1385 if (IS_ERR(pctl->irqmux[i])) in stm32_pctrl_dt_setup_irq()
1386 return PTR_ERR(pctl->irqmux[i]); in stm32_pctrl_dt_setup_irq()
1394 struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); in stm32_pctrl_build_state() local
1397 pctl->ngroups = pctl->npins; in stm32_pctrl_build_state()
1400 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1401 sizeof(*pctl->groups), GFP_KERNEL); in stm32_pctrl_build_state()
1402 if (!pctl->groups) in stm32_pctrl_build_state()
1403 return -ENOMEM; in stm32_pctrl_build_state()
1406 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, in stm32_pctrl_build_state()
1407 sizeof(*pctl->grp_names), GFP_KERNEL); in stm32_pctrl_build_state()
1408 if (!pctl->grp_names) in stm32_pctrl_build_state()
1409 return -ENOMEM; in stm32_pctrl_build_state()
1411 for (i = 0; i < pctl->npins; i++) { in stm32_pctrl_build_state()
1412 const struct stm32_desc_pin *pin = pctl->pins + i; in stm32_pctrl_build_state()
1413 struct stm32_pinctrl_group *group = pctl->groups + i; in stm32_pctrl_build_state()
1415 group->name = pin->pin.name; in stm32_pctrl_build_state()
1416 group->pin = pin->pin.number; in stm32_pctrl_build_state()
1417 pctl->grp_names[i] = pin->pin.name; in stm32_pctrl_build_state()
1423 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl, in stm32_pctrl_create_pins_tab() argument
1429 for (i = 0; i < pctl->match_data->npins; i++) { in stm32_pctrl_create_pins_tab()
1430 p = pctl->match_data->pins + i; in stm32_pctrl_create_pins_tab()
1431 if (pctl->pkg && !(pctl->pkg & p->pkg)) in stm32_pctrl_create_pins_tab()
1433 pins->pin = p->pin; in stm32_pctrl_create_pins_tab()
1434 pins->functions = p->functions; in stm32_pctrl_create_pins_tab()
1439 pctl->npins = nb_pins_available; in stm32_pctrl_create_pins_tab()
1445 struct stm32_pinctrl *pctl) in stm32_pctl_get_package() argument
1447 if (of_property_read_u32(np, "st,package", &pctl->pkg)) { in stm32_pctl_get_package()
1448 pctl->pkg = 0; in stm32_pctl_get_package()
1449 dev_warn(pctl->dev, "No package detected, use default one\n"); in stm32_pctl_get_package()
1451 dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg); in stm32_pctl_get_package()
1457 struct device_node *np = pdev->dev.of_node; in stm32_pctl_probe()
1460 struct device *dev = &pdev->dev; in stm32_pctl_probe()
1461 struct stm32_pinctrl *pctl; in stm32_pctl_probe() local
1466 return -EINVAL; in stm32_pctl_probe()
1468 match = of_match_device(dev->driver->of_match_table, dev); in stm32_pctl_probe()
1469 if (!match || !match->data) in stm32_pctl_probe()
1470 return -EINVAL; in stm32_pctl_probe()
1472 if (!of_find_property(np, "pins-are-numbered", NULL)) { in stm32_pctl_probe()
1473 dev_err(dev, "only support pins-are-numbered format\n"); in stm32_pctl_probe()
1474 return -EINVAL; in stm32_pctl_probe()
1477 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); in stm32_pctl_probe()
1478 if (!pctl) in stm32_pctl_probe()
1479 return -ENOMEM; in stm32_pctl_probe()
1481 platform_set_drvdata(pdev, pctl); in stm32_pctl_probe()
1484 pctl->domain = stm32_pctrl_get_irq_domain(np); in stm32_pctl_probe()
1485 if (IS_ERR(pctl->domain)) in stm32_pctl_probe()
1486 return PTR_ERR(pctl->domain); in stm32_pctl_probe()
1487 if (!pctl->domain) in stm32_pctl_probe()
1491 hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0); in stm32_pctl_probe()
1493 if (hwlock_id == -EPROBE_DEFER) in stm32_pctl_probe()
1496 pctl->hwlock = hwspin_lock_request_specific(hwlock_id); in stm32_pctl_probe()
1499 spin_lock_init(&pctl->irqmux_lock); in stm32_pctl_probe()
1501 pctl->dev = dev; in stm32_pctl_probe()
1502 pctl->match_data = match->data; in stm32_pctl_probe()
1505 stm32_pctl_get_package(np, pctl); in stm32_pctl_probe()
1507 pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins, in stm32_pctl_probe()
1508 sizeof(*pctl->pins), GFP_KERNEL); in stm32_pctl_probe()
1509 if (!pctl->pins) in stm32_pctl_probe()
1510 return -ENOMEM; in stm32_pctl_probe()
1512 ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins); in stm32_pctl_probe()
1519 return -EINVAL; in stm32_pctl_probe()
1522 if (pctl->domain) { in stm32_pctl_probe()
1523 ret = stm32_pctrl_dt_setup_irq(pdev, pctl); in stm32_pctl_probe()
1528 pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins), in stm32_pctl_probe()
1531 return -ENOMEM; in stm32_pctl_probe()
1533 for (i = 0; i < pctl->npins; i++) in stm32_pctl_probe()
1534 pins[i] = pctl->pins[i].pin; in stm32_pctl_probe()
1536 pctl->pctl_desc.name = dev_name(&pdev->dev); in stm32_pctl_probe()
1537 pctl->pctl_desc.owner = THIS_MODULE; in stm32_pctl_probe()
1538 pctl->pctl_desc.pins = pins; in stm32_pctl_probe()
1539 pctl->pctl_desc.npins = pctl->npins; in stm32_pctl_probe()
1540 pctl->pctl_desc.link_consumers = true; in stm32_pctl_probe()
1541 pctl->pctl_desc.confops = &stm32_pconf_ops; in stm32_pctl_probe()
1542 pctl->pctl_desc.pctlops = &stm32_pctrl_ops; in stm32_pctl_probe()
1543 pctl->pctl_desc.pmxops = &stm32_pmx_ops; in stm32_pctl_probe()
1544 pctl->dev = &pdev->dev; in stm32_pctl_probe()
1546 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, in stm32_pctl_probe()
1547 pctl); in stm32_pctl_probe()
1549 if (IS_ERR(pctl->pctl_dev)) { in stm32_pctl_probe()
1550 dev_err(&pdev->dev, "Failed pinctrl registration\n"); in stm32_pctl_probe()
1551 return PTR_ERR(pctl->pctl_dev); in stm32_pctl_probe()
1555 if (of_property_read_bool(child, "gpio-controller")) in stm32_pctl_probe()
1560 return -EINVAL; in stm32_pctl_probe()
1562 pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), in stm32_pctl_probe()
1564 if (!pctl->banks) in stm32_pctl_probe()
1565 return -ENOMEM; in stm32_pctl_probe()
1569 struct stm32_gpio_bank *bank = &pctl->banks[i]; in stm32_pctl_probe()
1571 if (of_property_read_bool(child, "gpio-controller")) { in stm32_pctl_probe()
1572 bank->rstc = of_reset_control_get_exclusive(child, in stm32_pctl_probe()
1574 if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) in stm32_pctl_probe()
1575 return -EPROBE_DEFER; in stm32_pctl_probe()
1577 bank->clk = of_clk_get_by_name(child, NULL); in stm32_pctl_probe()
1578 if (IS_ERR(bank->clk)) { in stm32_pctl_probe()
1579 if (PTR_ERR(bank->clk) != -EPROBE_DEFER) in stm32_pctl_probe()
1582 PTR_ERR(bank->clk)); in stm32_pctl_probe()
1583 return PTR_ERR(bank->clk); in stm32_pctl_probe()
1590 if (of_property_read_bool(child, "gpio-controller")) { in stm32_pctl_probe()
1591 ret = stm32_gpiolib_register_bank(pctl, child); in stm32_pctl_probe()
1597 pctl->nbanks++; in stm32_pctl_probe()
1607 struct stm32_pinctrl *pctl, u32 pin) in stm32_pinctrl_restore_gpio_regs() argument
1609 const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1616 range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin); in stm32_pinctrl_restore_gpio_regs()
1620 pin_is_irq = gpiochip_line_is_irq(range->gc, offset); in stm32_pinctrl_restore_gpio_regs()
1622 if (!desc || (!pin_is_irq && !desc->gpio_owner)) in stm32_pinctrl_restore_gpio_regs()
1625 bank = gpiochip_get_data(range->gc); in stm32_pinctrl_restore_gpio_regs()
1627 alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK; in stm32_pinctrl_restore_gpio_regs()
1629 mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK; in stm32_pinctrl_restore_gpio_regs()
1637 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL); in stm32_pinctrl_restore_gpio_regs()
1642 val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE); in stm32_pinctrl_restore_gpio_regs()
1648 val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK; in stm32_pinctrl_restore_gpio_regs()
1654 val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK; in stm32_pinctrl_restore_gpio_regs()
1661 regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr); in stm32_pinctrl_restore_gpio_regs()
1668 struct stm32_pinctrl *pctl = dev_get_drvdata(dev); in stm32_pinctrl_resume() local
1669 struct stm32_pinctrl_group *g = pctl->groups; in stm32_pinctrl_resume()
1672 for (i = 0; i < pctl->ngroups; i++, g++) in stm32_pinctrl_resume()
1673 stm32_pinctrl_restore_gpio_regs(pctl, g->pin); in stm32_pinctrl_resume()