Lines Matching +full:pwm +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
8 * - When changing both duty cycle and period, we cannot prevent in
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
18 #include <linux/pwm.h>
59 static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_sifive_request() argument
63 mutex_lock(&ddata->lock); in pwm_sifive_request()
64 ddata->user_count++; in pwm_sifive_request()
65 mutex_unlock(&ddata->lock); in pwm_sifive_request()
70 static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm) in pwm_sifive_free() argument
74 mutex_lock(&ddata->lock); in pwm_sifive_free()
75 ddata->user_count--; in pwm_sifive_free()
76 mutex_unlock(&ddata->lock); in pwm_sifive_free()
79 /* Called holding ddata->lock */
88 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the in pwm_sifive_update_clock()
94 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC); in pwm_sifive_update_clock()
95 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf); in pwm_sifive_update_clock()
99 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG); in pwm_sifive_update_clock()
103 ddata->real_period = div64_ul(num, rate); in pwm_sifive_update_clock()
104 dev_dbg(ddata->chip.dev, in pwm_sifive_update_clock()
105 "New real_period = %u ns\n", ddata->real_period); in pwm_sifive_update_clock()
108 static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm, in pwm_sifive_get_state() argument
114 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); in pwm_sifive_get_state()
116 state->enabled = duty > 0; in pwm_sifive_get_state()
118 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG); in pwm_sifive_get_state()
120 state->enabled = false; in pwm_sifive_get_state()
122 state->period = ddata->real_period; in pwm_sifive_get_state()
123 state->duty_cycle = in pwm_sifive_get_state()
124 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH; in pwm_sifive_get_state()
125 state->polarity = PWM_POLARITY_INVERSED; in pwm_sifive_get_state()
128 static int pwm_sifive_enable(struct pwm_chip *chip, bool enable) in pwm_sifive_enable() argument
133 if (enable) { in pwm_sifive_enable()
134 ret = clk_enable(ddata->clk); in pwm_sifive_enable()
136 dev_err(ddata->chip.dev, "Enable clk failed\n"); in pwm_sifive_enable()
141 if (!enable) in pwm_sifive_enable()
142 clk_disable(ddata->clk); in pwm_sifive_enable()
147 static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm, in pwm_sifive_apply() argument
158 if (state->polarity != PWM_POLARITY_INVERSED) in pwm_sifive_apply()
159 return -EINVAL; in pwm_sifive_apply()
161 ret = clk_enable(ddata->clk); in pwm_sifive_apply()
163 dev_err(ddata->chip.dev, "Enable clk failed\n"); in pwm_sifive_apply()
167 cur_state = pwm->state; in pwm_sifive_apply()
170 duty_cycle = state->duty_cycle; in pwm_sifive_apply()
171 if (!state->enabled) in pwm_sifive_apply()
181 frac = DIV64_U64_ROUND_CLOSEST(num, state->period); in pwm_sifive_apply()
183 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); in pwm_sifive_apply()
185 mutex_lock(&ddata->lock); in pwm_sifive_apply()
186 if (state->period != ddata->approx_period) { in pwm_sifive_apply()
189 * However if ddate->approx_period == 0 this is the first time we set in pwm_sifive_apply()
193 if (ddata->user_count != 1 && ddata->approx_period) { in pwm_sifive_apply()
194 mutex_unlock(&ddata->lock); in pwm_sifive_apply()
195 ret = -EBUSY; in pwm_sifive_apply()
198 ddata->approx_period = state->period; in pwm_sifive_apply()
199 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk)); in pwm_sifive_apply()
201 mutex_unlock(&ddata->lock); in pwm_sifive_apply()
203 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); in pwm_sifive_apply()
205 if (state->enabled != enabled) in pwm_sifive_apply()
206 pwm_sifive_enable(chip, state->enabled); in pwm_sifive_apply()
209 clk_disable(ddata->clk); in pwm_sifive_apply()
229 mutex_lock(&ddata->lock); in pwm_sifive_clock_notifier()
230 pwm_sifive_update_clock(ddata, ndata->new_rate); in pwm_sifive_clock_notifier()
231 mutex_unlock(&ddata->lock); in pwm_sifive_clock_notifier()
239 struct device *dev = &pdev->dev; in pwm_sifive_probe()
249 return -ENOMEM; in pwm_sifive_probe()
251 mutex_init(&ddata->lock); in pwm_sifive_probe()
252 chip = &ddata->chip; in pwm_sifive_probe()
253 chip->dev = dev; in pwm_sifive_probe()
254 chip->ops = &pwm_sifive_ops; in pwm_sifive_probe()
255 chip->of_xlate = of_pwm_xlate_with_flags; in pwm_sifive_probe()
256 chip->of_pwm_n_cells = 3; in pwm_sifive_probe()
257 chip->base = -1; in pwm_sifive_probe()
258 chip->npwm = 4; in pwm_sifive_probe()
261 ddata->regs = devm_ioremap_resource(dev, res); in pwm_sifive_probe()
262 if (IS_ERR(ddata->regs)) in pwm_sifive_probe()
263 return PTR_ERR(ddata->regs); in pwm_sifive_probe()
265 ddata->clk = devm_clk_get(dev, NULL); in pwm_sifive_probe()
266 if (IS_ERR(ddata->clk)) in pwm_sifive_probe()
267 return dev_err_probe(dev, PTR_ERR(ddata->clk), in pwm_sifive_probe()
270 ret = clk_prepare_enable(ddata->clk); in pwm_sifive_probe()
272 dev_err(dev, "failed to enable clock for pwm: %d\n", ret); in pwm_sifive_probe()
276 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG); in pwm_sifive_probe()
280 for (i = 0; i < chip->npwm; ++i) { in pwm_sifive_probe()
281 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i)); in pwm_sifive_probe()
287 /* The clk should be on once for each running PWM. */ in pwm_sifive_probe()
291 ret = clk_enable(ddata->clk); in pwm_sifive_probe()
293 dev_err_probe(dev, ret, "Failed to enable clk\n"); in pwm_sifive_probe()
299 clk_disable(ddata->clk); in pwm_sifive_probe()
304 ddata->notifier.notifier_call = pwm_sifive_clock_notifier; in pwm_sifive_probe()
305 ret = clk_notifier_register(ddata->clk, &ddata->notifier); in pwm_sifive_probe()
313 dev_err(dev, "cannot register PWM: %d\n", ret); in pwm_sifive_probe()
318 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm); in pwm_sifive_probe()
323 clk_notifier_unregister(ddata->clk, &ddata->notifier); in pwm_sifive_probe()
326 clk_disable(ddata->clk); in pwm_sifive_probe()
327 --enabled_clks; in pwm_sifive_probe()
329 clk_unprepare(ddata->clk); in pwm_sifive_probe()
337 struct pwm_device *pwm; in pwm_sifive_remove() local
340 pwmchip_remove(&ddata->chip); in pwm_sifive_remove()
341 clk_notifier_unregister(ddata->clk, &ddata->notifier); in pwm_sifive_remove()
343 for (ch = 0; ch < ddata->chip.npwm; ch++) { in pwm_sifive_remove()
344 pwm = &ddata->chip.pwms[ch]; in pwm_sifive_remove()
345 if (pwm->state.enabled) in pwm_sifive_remove()
346 clk_disable(ddata->clk); in pwm_sifive_remove()
349 clk_unprepare(ddata->clk); in pwm_sifive_remove()
364 .name = "pwm-sifive",
370 MODULE_DESCRIPTION("SiFive PWM driver");