1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <linux/pwm.h>
42 			       unsigned int offset)  in zx_pwm_readl()  argument
44 	return readl(zpc->base + (hwpwm + 1) * 0x10 + offset);  in zx_pwm_readl()
48 				 unsigned int offset, u32 value)  in zx_pwm_writel()  argument
50 	writel(value, zpc->base + (hwpwm + 1) * 0x10 + offset);  in zx_pwm_writel()
54 			    unsigned int offset, u32 mask, u32 value)  in zx_pwm_set_mask()  argument
58 	data = zx_pwm_readl(zpc, hwpwm, offset);  in zx_pwm_set_mask()
61 	zx_pwm_writel(zpc, hwpwm, offset, data);  in zx_pwm_set_mask()
64 static void zx_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in zx_pwm_get_state()  argument
73 	value = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_MODE);  in zx_pwm_get_state()
76 		state->polarity = PWM_POLARITY_NORMAL;  in zx_pwm_get_state()
78 		state->polarity = PWM_POLARITY_INVERSED;  in zx_pwm_get_state()
81 		state->enabled = true;  in zx_pwm_get_state()
83 		state->enabled = false;  in zx_pwm_get_state()
86 	rate = clk_get_rate(zpc->wclk);  in zx_pwm_get_state()
88 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_PERIOD);  in zx_pwm_get_state()
90 	state->period = DIV_ROUND_CLOSEST_ULL(tmp, rate);  in zx_pwm_get_state()
92 	tmp = zx_pwm_readl(zpc, pwm->hwpwm, ZX_PWM_DUTY);  in zx_pwm_get_state()
94 	state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, rate);  in zx_pwm_get_state()
97 static int zx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,  in zx_pwm_config()  argument
107 	rate = clk_get_rate(zpc->wclk);  in zx_pwm_config()
120 			return -ERANGE;  in zx_pwm_config()
130 	 * If the PWM is being enabled, we have to temporarily disable it  in zx_pwm_config()
133 	if (pwm_is_enabled(pwm))  in zx_pwm_config()
134 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_EN, 0);  in zx_pwm_config()
137 	zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_CLKDIV_MASK,  in zx_pwm_config()
139 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_PERIOD, period_cycles);  in zx_pwm_config()
140 	zx_pwm_writel(zpc, pwm->hwpwm, ZX_PWM_DUTY, duty_cycles);  in zx_pwm_config()
142 	/* Re-enable the PWM if needed */  in zx_pwm_config()
143 	if (pwm_is_enabled(pwm))  in zx_pwm_config()
144 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_config()
150 static int zx_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in zx_pwm_apply()  argument
157 	pwm_get_state(pwm, &cstate);  in zx_pwm_apply()
159 	if (state->polarity != cstate.polarity)  in zx_pwm_apply()
160 		zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE, ZX_PWM_POLAR,  in zx_pwm_apply()
161 				(state->polarity == PWM_POLARITY_INVERSED) ?  in zx_pwm_apply()
164 	if (state->period != cstate.period ||  in zx_pwm_apply()
165 	    state->duty_cycle != cstate.duty_cycle) {  in zx_pwm_apply()
166 		ret = zx_pwm_config(chip, pwm, state->duty_cycle,  in zx_pwm_apply()
167 				    state->period);  in zx_pwm_apply()
172 	if (state->enabled != cstate.enabled) {  in zx_pwm_apply()
173 		if (state->enabled) {  in zx_pwm_apply()
174 			ret = clk_prepare_enable(zpc->wclk);  in zx_pwm_apply()
178 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_apply()
181 			zx_pwm_set_mask(zpc, pwm->hwpwm, ZX_PWM_MODE,  in zx_pwm_apply()
183 			clk_disable_unprepare(zpc->wclk);  in zx_pwm_apply()
203 	zpc = devm_kzalloc(&pdev->dev, sizeof(*zpc), GFP_KERNEL);  in zx_pwm_probe()
205 		return -ENOMEM;  in zx_pwm_probe()
208 	zpc->base = devm_ioremap_resource(&pdev->dev, res);  in zx_pwm_probe()
209 	if (IS_ERR(zpc->base))  in zx_pwm_probe()
210 		return PTR_ERR(zpc->base);  in zx_pwm_probe()
212 	zpc->pclk = devm_clk_get(&pdev->dev, "pclk");  in zx_pwm_probe()
213 	if (IS_ERR(zpc->pclk))  in zx_pwm_probe()
214 		return PTR_ERR(zpc->pclk);  in zx_pwm_probe()
216 	zpc->wclk = devm_clk_get(&pdev->dev, "wclk");  in zx_pwm_probe()
217 	if (IS_ERR(zpc->wclk))  in zx_pwm_probe()
218 		return PTR_ERR(zpc->wclk);  in zx_pwm_probe()
220 	ret = clk_prepare_enable(zpc->pclk);  in zx_pwm_probe()
224 	zpc->chip.dev = &pdev->dev;  in zx_pwm_probe()
225 	zpc->chip.ops = &zx_pwm_ops;  in zx_pwm_probe()
226 	zpc->chip.base = -1;  in zx_pwm_probe()
227 	zpc->chip.npwm = 4;  in zx_pwm_probe()
228 	zpc->chip.of_xlate = of_pwm_xlate_with_flags;  in zx_pwm_probe()
229 	zpc->chip.of_pwm_n_cells = 3;  in zx_pwm_probe()
232 	 * PWM devices may be enabled by firmware, and let's disable all of  in zx_pwm_probe()
235 	for (i = 0; i < zpc->chip.npwm; i++)  in zx_pwm_probe()
238 	ret = pwmchip_add(&zpc->chip);  in zx_pwm_probe()
240 		dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);  in zx_pwm_probe()
241 		clk_disable_unprepare(zpc->pclk);  in zx_pwm_probe()
255 	ret = pwmchip_remove(&zpc->chip);  in zx_pwm_remove()
256 	clk_disable_unprepare(zpc->pclk);  in zx_pwm_remove()
262 	{ .compatible = "zte,zx296718-pwm", },
269 		.name = "zx-pwm",
277 MODULE_ALIAS("platform:zx-pwm");
279 MODULE_DESCRIPTION("ZTE ZX PWM Driver");