Lines Matching +full:0 +full:x261
23 #define FALSE 0
37 #define OEM_ID_ICP 0x941c
38 #define OEM_ID_INTEL 0x8000
41 #define GDT_PCI 0x03 /* PCI controller */
42 #define GDT_PCINEW 0x04 /* new PCI controller */
43 #define GDT_PCIMPR 0x05 /* PCI MPR controller */
47 #define PCI_DEVICE_ID_VORTEX_GDT60x0 0 /* GDT6000/6020/6050 */
68 #define PCI_DEVICE_ID_VORTEX_GDT6x17RP 0x100 /* GDT6117RP/GDT6517RP */
69 #define PCI_DEVICE_ID_VORTEX_GDT6x27RP 0x101 /* GDT6127RP/GDT6527RP */
70 #define PCI_DEVICE_ID_VORTEX_GDT6537RP 0x102 /* GDT6537RP */
71 #define PCI_DEVICE_ID_VORTEX_GDT6557RP 0x103 /* GDT6557RP */
73 #define PCI_DEVICE_ID_VORTEX_GDT6x11RP 0x104 /* GDT6111RP/GDT6511RP */
74 #define PCI_DEVICE_ID_VORTEX_GDT6x21RP 0x105 /* GDT6121RP/GDT6521RP */
78 #define PCI_DEVICE_ID_VORTEX_GDT6x17RD 0x110 /* GDT6117RD/GDT6517RD */
79 #define PCI_DEVICE_ID_VORTEX_GDT6x27RD 0x111 /* GDT6127RD/GDT6527RD */
80 #define PCI_DEVICE_ID_VORTEX_GDT6537RD 0x112 /* GDT6537RD */
81 #define PCI_DEVICE_ID_VORTEX_GDT6557RD 0x113 /* GDT6557RD */
83 #define PCI_DEVICE_ID_VORTEX_GDT6x11RD 0x114 /* GDT6111RD/GDT6511RD */
84 #define PCI_DEVICE_ID_VORTEX_GDT6x21RD 0x115 /* GDT6121RD/GDT6521RD */
86 #define PCI_DEVICE_ID_VORTEX_GDT6x18RD 0x118 /* GDT6118RD/GDT6518RD/
88 #define PCI_DEVICE_ID_VORTEX_GDT6x28RD 0x119 /* GDT6128RD/GDT6528RD/
90 #define PCI_DEVICE_ID_VORTEX_GDT6x38RD 0x11A /* GDT6538RD/GDT6638RD */
91 #define PCI_DEVICE_ID_VORTEX_GDT6x58RD 0x11B /* GDT6558RD/GDT6658RD */
93 #define PCI_DEVICE_ID_VORTEX_GDT7x18RN 0x168 /* GDT7118RN/GDT7518RN/
95 #define PCI_DEVICE_ID_VORTEX_GDT7x28RN 0x169 /* GDT7128RN/GDT7528RN/
97 #define PCI_DEVICE_ID_VORTEX_GDT7x38RN 0x16A /* GDT7538RN/GDT7638RN */
98 #define PCI_DEVICE_ID_VORTEX_GDT7x58RN 0x16B /* GDT7558RN/GDT7658RN */
103 #define PCI_DEVICE_ID_VORTEX_GDT6x19RD 0x210 /* GDT6519RD/GDT6619RD */
104 #define PCI_DEVICE_ID_VORTEX_GDT6x29RD 0x211 /* GDT6529RD/GDT6629RD */
106 #define PCI_DEVICE_ID_VORTEX_GDT7x19RN 0x260 /* GDT7519RN/GDT7619RN */
107 #define PCI_DEVICE_ID_VORTEX_GDT7x29RN 0x261 /* GDT7529RN/GDT7629RN */
112 #define PCI_DEVICE_ID_VORTEX_GDTMAXRP 0x2ff
117 #define PCI_DEVICE_ID_VORTEX_GDTNEWRX 0x300
122 #define PCI_DEVICE_ID_VORTEX_GDTNEWRX2 0x301
127 #define PCI_DEVICE_ID_INTEL_SRC 0x600
132 #define PCI_DEVICE_ID_INTEL_SRC_XSCALE 0x601
171 #define MSG_REQUEST 0 /* async. event: message */
174 #define DPMEM_MAGIC 0xC0FFEE11
186 #define GDT_INIT 0 /* service initialization */
226 #define SCSI_DR_INFO 0x00 /* SCSI drive info */
227 #define SCSI_CHAN_CNT 0x05 /* SCSI channel count */
228 #define SCSI_DR_LIST 0x06 /* SCSI drive list */
229 #define SCSI_DEF_CNT 0x15 /* grown/primary defects */
230 #define DSK_STATISTICS 0x4b /* SCSI disk statistics */
231 #define IOCHAN_DESC 0x5d /* description of IO channel */
232 #define IOCHAN_RAW_DESC 0x5e /* description of raw IO chn. */
233 #define L_CTRL_PATTERN 0x20000000L /* SCSI IOCTL mask */
234 #define ARRAY_INFO 0x12 /* array drive info */
235 #define ARRAY_DRV_LIST 0x0f /* array drive list */
236 #define ARRAY_DRV_LIST2 0x34 /* array drive list (new) */
237 #define LA_CTRL_PATTERN 0x10000000L /* array IOCTL mask */
238 #define CACHE_DRV_CNT 0x01 /* cache drive count */
239 #define CACHE_DRV_LIST 0x02 /* cache drive list */
240 #define CACHE_INFO 0x04 /* cache info */
241 #define CACHE_CONFIG 0x05 /* cache configuration */
242 #define CACHE_DRV_INFO 0x07 /* cache drive info */
243 #define BOARD_FEATURES 0x15 /* controller features */
244 #define BOARD_INFO 0x28 /* controller info */
245 #define SET_PERF_MODES 0x82 /* set mode (coalescing,..) */
246 #define GET_PERF_MODES 0x83 /* get mode */
247 #define CACHE_READ_OEM_STRING_RECORD 0x84 /* read OEM string record */
248 #define HOST_GET 0x10001L /* get host drive list */
249 #define IO_CHANNEL 0x00020000L /* default IO channel */
250 #define INVALID_CHANNEL 0x0000ffffL /* invalid channel */
258 #define S_RAW_ILL 0xff /* raw serv.: illegal */
268 #define DEFAULT_PRI 0x20
269 #define IOCTL_PRI 0x10
270 #define HIGH_PRI 0x08
273 #define GDTH_DATA_IN 0x01000000L /* data from target */
274 #define GDTH_DATA_OUT 0x00000000L /* data to target */
278 #define SECS32 0x1f /* round capacity */
279 #define BIOS_ID_OFFS 0x10 /* offset contr-ID in ISABIOS */
280 #define LOCALBOARD 0 /* board node always 0 */
281 #define ASYNCINDEX 0 /* cmd index async. event */
287 #define GDT_WR_THROUGH 0x100 /* WRITE_THROUGH supported */
288 #define GDT_64BIT 0x200 /* 64bit / drv>2TB support */
317 u32 st_mode; /* 0=dis., 1=st_buf_addr1 valid, 2=both */
325 u32 cmd_mode; /* 0 = mode disabled, 1 = cmd_buff_addr1 */
398 u8 sddc_type; /* 0x08: grown, 0x10: prim. */
433 u32 list_offset; /* offset of list[0] */
599 u8 striping; /* Striping (RAID-0) supp. */
694 u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
700 u8 bios_area[0x4000]; /* 16KB reserved for BIOS */
704 u8 if_area[0x3000]; /* 12KB for interface */
720 u8 if_area[0xff0-sizeof(gdt_pci_sram)];
738 u8 cfg_reg; /* DPRAM cfg.(2:below 1MB,0:anywhere)*/
739 u8 unused1[0x3f];
746 u8 unused3[0x10];
753 u8 unused6[0x16];
760 u8 if_area[0x4000-sizeof(gdt_pci_sram)];
791 u8 if_area[0x3000-sizeof(gdt_pci_sram)];
885 } cmndinfo[GDTH_MAXCMDS]; /* index==0 is free */