Lines Matching +full:double +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
96 u8 phase; member
153 enum mesh_phase phase; /* what we're currently trying to do */ member
215 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in dlog()
218 tlp = &tp->log[tp->log_ix]; in dlog()
219 slp = &ms->log[ms->log_ix]; in dlog()
220 tlp->fmt = fmt; in dlog()
221 tlp->tb = readtb(); in dlog()
222 tlp->phase = (ms->msgphase << 4) + ms->phase; in dlog()
223 tlp->bs0 = ms->mesh->bus_status0; in dlog()
224 tlp->bs1 = ms->mesh->bus_status1; in dlog()
225 tlp->tgt = ms->conn_tgt; in dlog()
226 tlp->d = a; in dlog()
228 if (++tp->log_ix >= N_DBG_LOG) in dlog()
229 tp->log_ix = 0; in dlog()
230 if (tp->n_log < N_DBG_LOG) in dlog()
231 ++tp->n_log; in dlog()
232 if (++ms->log_ix >= N_DBG_SLOG) in dlog()
233 ms->log_ix = 0; in dlog()
234 if (ms->n_log < N_DBG_SLOG) in dlog()
235 ++ms->n_log; in dlog()
240 struct mesh_target *tp = &ms->tgts[t]; in dumplog()
244 if (tp->n_log == 0) in dumplog()
246 i = tp->log_ix - tp->n_log; in dumplog()
249 tp->n_log = 0; in dumplog()
251 lp = &tp->log[i]; in dumplog()
253 t, lp->bs1, lp->bs0, lp->phase); in dumplog()
255 printk("tb=%10u ", lp->tb); in dumplog()
257 printk(lp->fmt, lp->d); in dumplog()
261 } while (i != tp->log_ix); in dumplog()
269 if (ms->n_log == 0) in dumpslog()
271 i = ms->log_ix - ms->n_log; in dumpslog()
274 ms->n_log = 0; in dumpslog()
276 lp = &ms->log[i]; in dumpslog()
278 lp->bs1, lp->bs0, lp->phase, lp->tgt); in dumpslog()
280 printk("tb=%10u ", lp->tb); in dumpslog()
282 printk(lp->fmt, lp->d); in dumpslog()
286 } while (i != ms->log_ix); in dumpslog()
305 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs()
306 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_dump_regs()
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
317 mr->sync_params); in mesh_dump_regs()
318 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
321 in_le32(&md->status), in_le32(&md->cmdptr)); in mesh_dump_regs()
322 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n", in mesh_dump_regs()
323 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); in mesh_dump_regs()
325 ms->dma_started, ms->dma_count, ms->n_msgout); in mesh_dump_regs()
327 tp = &ms->tgts[t]; in mesh_dump_regs()
328 if (tp->current_req == NULL) in mesh_dump_regs()
331 t, tp->current_req, tp->data_goes_out, tp->saved_ptr); in mesh_dump_regs()
341 (void)in_8(&mr->mesh_id); in mesh_flush_io()
350 (*cmd->scsi_done)(cmd); in mesh_completed()
360 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init()
361 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_init()
367 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_init()
368 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
369 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
370 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
373 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
374 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
375 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
376 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
382 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
385 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
393 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
394 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
397 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
398 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
400 ms->phase = idle; in mesh_init()
401 ms->msgphase = msg_none; in mesh_init()
407 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd()
410 id = cmd->device->id; in mesh_start_cmd()
411 ms->current_req = cmd; in mesh_start_cmd()
412 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE; in mesh_start_cmd()
413 ms->tgts[id].current_req = cmd; in mesh_start_cmd()
419 for (i = 0; i < cmd->cmd_len; ++i) in mesh_start_cmd()
420 printk(" %x", cmd->cmnd[i]); in mesh_start_cmd()
425 if (ms->dma_started) in mesh_start_cmd()
426 panic("mesh: double DMA start !\n"); in mesh_start_cmd()
428 ms->phase = arbitrating; in mesh_start_cmd()
429 ms->msgphase = msg_none; in mesh_start_cmd()
430 ms->data_ptr = 0; in mesh_start_cmd()
431 ms->dma_started = 0; in mesh_start_cmd()
432 ms->n_msgout = 0; in mesh_start_cmd()
433 ms->last_n_msgout = 0; in mesh_start_cmd()
434 ms->expect_reply = 0; in mesh_start_cmd()
435 ms->conn_tgt = id; in mesh_start_cmd()
436 ms->tgts[id].saved_ptr = 0; in mesh_start_cmd()
437 ms->stat = DID_OK; in mesh_start_cmd()
438 ms->aborting = 0; in mesh_start_cmd()
440 ms->tgts[id].n_log = 0; in mesh_start_cmd()
446 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
447 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
448 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
452 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
454 * Some other device has the bus or is arbitrating for it - in mesh_start_cmd()
458 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
459 mr->error, mr->fifo_count)); in mesh_start_cmd()
460 for (t = 100; t > 0; --t) { in mesh_start_cmd()
461 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
463 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
465 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
466 mr->error, mr->fifo_count)); in mesh_start_cmd()
468 if (ms->phase != arbitrating) in mesh_start_cmd()
473 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
475 ms->stat = DID_BUS_BUSY; in mesh_start_cmd()
476 ms->phase = idle; in mesh_start_cmd()
486 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
500 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
501 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
503 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
504 mr->error, mr->fifo_count)); in mesh_start_cmd()
506 if (ms->phase != arbitrating) in mesh_start_cmd()
509 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
510 mr->error, mr->fifo_count)); in mesh_start_cmd()
513 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
515 for (t = 230; t > 0; --t) { in mesh_start_cmd()
516 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
521 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
522 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
523 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
524 /* looks like a reselection - try resetting the mesh */ in mesh_start_cmd()
526 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
527 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
530 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
531 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
532 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
534 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
537 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
539 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
540 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
562 if (ms->phase != idle || ms->current_req != NULL) { in mesh_start()
563 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)", in mesh_start()
564 ms->phase, ms); in mesh_start()
568 while (ms->phase == idle) { in mesh_start()
570 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) { in mesh_start()
573 if (ms->tgts[cmd->device->id].current_req == NULL) in mesh_start()
577 next = (struct scsi_cmnd *) cmd->host_scribble; in mesh_start()
579 ms->request_q = next; in mesh_start()
581 prev->host_scribble = (void *) next; in mesh_start()
583 ms->request_qtail = prev; in mesh_start()
592 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in mesh_done()
594 cmd = ms->current_req; in mesh_done()
595 ms->current_req = NULL; in mesh_done()
596 tp->current_req = NULL; in mesh_done()
598 cmd->result = (ms->stat << 16) | cmd->SCp.Status; in mesh_done()
599 if (ms->stat == DID_OK) in mesh_done()
600 cmd->result |= cmd->SCp.Message << 8; in mesh_done()
603 cmd->result, ms->data_ptr, scsi_bufflen(cmd)); in mesh_done()
606 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3) in mesh_done()
607 && cmd->request_buffer != 0) { in mesh_done()
608 unsigned char *b = cmd->request_buffer; in mesh_done()
614 cmd->SCp.this_residual -= ms->data_ptr; in mesh_done()
618 out_8(&ms->mesh->sequence, SEQ_ENBRESEL); in mesh_done()
619 mesh_flush_io(ms->mesh); in mesh_done()
621 ms->phase = idle; in mesh_done()
628 int i = ms->n_msgout; in add_sdtr_msg()
630 ms->msgout[i] = EXTENDED_MESSAGE; in add_sdtr_msg()
631 ms->msgout[i+1] = 3; in add_sdtr_msg()
632 ms->msgout[i+2] = EXTENDED_SDTR; in add_sdtr_msg()
633 ms->msgout[i+3] = mesh_sync_period/4; in add_sdtr_msg()
634 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0); in add_sdtr_msg()
635 ms->n_msgout = i + 5; in add_sdtr_msg()
640 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in set_sdtr()
641 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr()
644 tp->sdtr_state = sdtr_done; in set_sdtr()
647 if (SYNC_OFF(tp->sync_params)) in set_sdtr()
649 ms->conn_tgt); in set_sdtr()
650 tp->sync_params = ASYNC_PARAMS; in set_sdtr()
651 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
655 * We need to compute ceil(clk_freq * period / 500e6) - 2 in set_sdtr()
658 v = (ms->clk_freq / 5000) * period; in set_sdtr()
663 tr = (ms->clk_freq + 250000) / 500000; in set_sdtr()
666 v = (v + 99999) / 100000 - 2; in set_sdtr()
669 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000; in set_sdtr()
673 tp->sync_params = SYNC_PARAMS(offset, v); in set_sdtr()
674 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
676 ms->conn_tgt, tr/10, tr%10); in set_sdtr()
682 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase()
683 volatile struct dbdma_regs __iomem *md = ms->dma; in start_phase()
684 struct scsi_cmnd *cmd = ms->current_req; in start_phase()
685 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in start_phase()
688 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
689 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
690 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in start_phase()
691 switch (ms->msgphase) { in start_phase()
696 out_8(&mr->count_hi, 0); in start_phase()
697 out_8(&mr->count_lo, 1); in start_phase()
698 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
699 ms->n_msgin = 0; in start_phase()
708 if (ms->n_msgout <= 0) { in start_phase()
710 ms->n_msgout); in start_phase()
712 ms->msgphase = msg_none; in start_phase()
715 if (ALLOW_DEBUG(ms->conn_tgt)) { in start_phase()
717 ms->n_msgout); in start_phase()
718 for (i = 0; i < ms->n_msgout; ++i) in start_phase()
719 printk(" %x", ms->msgout[i]); in start_phase()
722 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0], in start_phase()
723 ms->msgout[1], ms->msgout[2])); in start_phase()
724 out_8(&mr->count_hi, 0); in start_phase()
725 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
732 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
733 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
734 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
737 out_8(&mr->count_lo, 1); in start_phase()
738 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
739 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
740 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
742 if (ms->n_msgout == 1) { in start_phase()
751 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
752 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
753 for (i = 0; i < ms->n_msgout - 1; ++i) in start_phase()
754 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
760 ms->msgphase); in start_phase()
763 switch (ms->phase) { in start_phase()
765 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
766 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
769 out_8(&mr->sync_params, tp->sync_params); in start_phase()
770 out_8(&mr->count_hi, 0); in start_phase()
772 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
773 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
774 for (i = 0; i < cmd->cmd_len; ++i) in start_phase()
775 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
777 out_8(&mr->count_lo, 6); in start_phase()
778 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
780 out_8(&mr->fifo, 0); in start_phase()
785 if (!ms->dma_started) { in start_phase()
787 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds)); in start_phase()
788 out_le32(&md->control, (RUN << 16) | RUN); in start_phase()
789 ms->dma_started = 1; in start_phase()
791 nb = ms->dma_count; in start_phase()
794 ms->dma_count -= nb; in start_phase()
795 ms->data_ptr += nb; in start_phase()
796 out_8(&mr->count_lo, nb); in start_phase()
797 out_8(&mr->count_hi, nb >> 8); in start_phase()
798 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
802 out_8(&mr->count_hi, 0); in start_phase()
803 out_8(&mr->count_lo, 1); in start_phase()
804 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
808 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
812 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
813 mr->fifo_count)); in start_phase()
814 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
817 printk(KERN_ERR "mesh: start_phase called with phase=%d\n", in start_phase()
818 ms->phase); in start_phase()
826 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin()
829 n = mr->fifo_count; in get_msgin()
831 i = ms->n_msgin; in get_msgin()
832 ms->n_msgin = i + n; in get_msgin()
833 for (; n > 0; --n) in get_msgin()
834 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
843 if (ms->n_msgin > 0) { in msgin_length()
844 b = ms->msgin[0]; in msgin_length()
847 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2; in msgin_length()
849 /* 2-byte message */ in msgin_length()
858 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected()
863 switch (ms->phase) { in reselected()
867 if ((cmd = ms->current_req) != NULL) { in reselected()
869 cmd->host_scribble = (void *) ms->request_q; in reselected()
870 if (ms->request_q == NULL) in reselected()
871 ms->request_qtail = cmd; in reselected()
872 ms->request_q = cmd; in reselected()
873 tp = &ms->tgts[cmd->device->id]; in reselected()
874 tp->current_req = NULL; in reselected()
878 ms->phase = reselecting; in reselected()
884 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n", in reselected()
885 ms->msgphase, ms->phase, ms->conn_tgt); in reselected()
886 dumplog(ms, ms->conn_tgt); in reselected()
890 if (ms->dma_started) { in reselected()
894 ms->current_req = NULL; in reselected()
895 ms->phase = dataing; in reselected()
896 ms->msgphase = msg_in; in reselected()
897 ms->n_msgout = 0; in reselected()
898 ms->last_n_msgout = 0; in reselected()
899 prev = ms->conn_tgt; in reselected()
904 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
907 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
910 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
914 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
916 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
919 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
922 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
927 if (in_8(&mr->fifo_count) == 0) { in reselected()
929 ms->conn_tgt = ms->host->this_id; in reselected()
934 b = in_8(&mr->fifo); in reselected()
936 } while (in_8(&mr->fifo_count)); in reselected()
938 if ((b & (1 << t)) != 0 && t != ms->host->this_id) in reselected()
940 if (b != (1 << t) + (1 << ms->host->this_id)) { in reselected()
942 ms->conn_tgt = ms->host->this_id; in reselected()
950 ms->conn_tgt = t; in reselected()
951 tp = &ms->tgts[t]; in reselected()
952 out_8(&mr->sync_params, tp->sync_params); in reselected()
956 tp->saved_ptr, tp->data_goes_out, tp->current_req); in reselected()
958 ms->current_req = tp->current_req; in reselected()
959 if (tp->current_req == NULL) { in reselected()
963 ms->data_ptr = tp->saved_ptr; in reselected()
965 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
970 dumplog(ms, ms->conn_tgt); in reselected()
972 ms->data_ptr = 0; in reselected()
973 ms->aborting = 1; in reselected()
979 ms->msgout[0] = ABORT; in do_abort()
980 ms->n_msgout = 1; in do_abort()
981 ms->aborting = 1; in do_abort()
982 ms->stat = DID_ABORT; in do_abort()
991 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset()
994 tp = &ms->tgts[tgt]; in handle_reset()
995 if ((cmd = tp->current_req) != NULL) { in handle_reset()
996 cmd->result = DID_RESET << 16; in handle_reset()
997 tp->current_req = NULL; in handle_reset()
1000 ms->tgts[tgt].sdtr_state = do_sdtr; in handle_reset()
1001 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in handle_reset()
1003 ms->current_req = NULL; in handle_reset()
1004 while ((cmd = ms->request_q) != NULL) { in handle_reset()
1005 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble; in handle_reset()
1006 cmd->result = DID_RESET << 16; in handle_reset()
1009 ms->phase = idle; in handle_reset()
1010 ms->msgphase = msg_none; in handle_reset()
1011 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1012 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1015 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1016 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1023 struct Scsi_Host *dev = ms->host; in do_mesh_interrupt()
1025 spin_lock_irqsave(dev->host_lock, flags); in do_mesh_interrupt()
1027 spin_unlock_irqrestore(dev->host_lock, flags); in do_mesh_interrupt()
1034 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error()
1036 err = in_8(&mr->error); in handle_error()
1037 exc = in_8(&mr->exception); in handle_error()
1038 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1040 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1045 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1048 if (ms->dma_started) in handle_error()
1060 if (!ms->aborting) { in handle_error()
1062 ms->conn_tgt); in handle_error()
1063 dumplog(ms, ms->conn_tgt); in handle_error()
1066 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1067 ms->stat = DID_ABORT; in handle_error()
1072 if (ms->msgphase == msg_in) { in handle_error()
1074 ms->conn_tgt); in handle_error()
1075 ms->msgout[0] = MSG_PARITY_ERROR; in handle_error()
1076 ms->n_msgout = 1; in handle_error()
1077 ms->msgphase = msg_in_bad; in handle_error()
1081 if (ms->stat == DID_OK) { in handle_error()
1083 ms->conn_tgt); in handle_error()
1084 ms->stat = DID_PARITY; in handle_error()
1086 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1091 out_8(&mr->sequence, mr->sequence); in handle_error()
1116 dumplog(ms, ms->conn_tgt); in handle_error()
1117 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1123 ms->stat = DID_ERROR; in handle_error()
1130 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception()
1132 exc = in_8(&mr->exception); in handle_exception()
1133 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1140 ms->stat = DID_BUS_BUSY; in handle_exception()
1144 ms->stat = DID_BAD_TARGET; in handle_exception()
1153 dumplog(ms, ms->conn_tgt); in handle_exception()
1162 struct scsi_cmnd *cmd = ms->current_req; in handle_msgin()
1163 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in handle_msgin()
1165 if (ms->n_msgin == 0) in handle_msgin()
1167 code = ms->msgin[0]; in handle_msgin()
1168 if (ALLOW_DEBUG(ms->conn_tgt)) { in handle_msgin()
1169 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin); in handle_msgin()
1170 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1171 printk(" %x", ms->msgin[i]); in handle_msgin()
1175 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2])); in handle_msgin()
1177 ms->expect_reply = 0; in handle_msgin()
1178 ms->n_msgout = 0; in handle_msgin()
1179 if (ms->n_msgin < msgin_length(ms)) in handle_msgin()
1182 cmd->SCp.Message = code; in handle_msgin()
1187 switch (ms->msgin[2]) { in handle_msgin()
1189 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6] in handle_msgin()
1190 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8); in handle_msgin()
1193 if (tp->sdtr_state != sdtr_sent) { in handle_msgin()
1198 if (ms->msgout[3] < ms->msgin[3]) in handle_msgin()
1199 ms->msgout[3] = ms->msgin[3]; in handle_msgin()
1200 if (ms->msgout[4] > ms->msgin[4]) in handle_msgin()
1201 ms->msgout[4] = ms->msgin[4]; in handle_msgin()
1202 set_sdtr(ms, ms->msgout[3], ms->msgout[4]); in handle_msgin()
1203 ms->msgphase = msg_out; in handle_msgin()
1205 set_sdtr(ms, ms->msgin[3], ms->msgin[4]); in handle_msgin()
1213 tp->saved_ptr = ms->data_ptr; in handle_msgin()
1216 ms->data_ptr = tp->saved_ptr; in handle_msgin()
1219 ms->phase = disconnecting; in handle_msgin()
1224 if (tp->sdtr_state == sdtr_sent) in handle_msgin()
1233 ms->msgphase = msg_out; in handle_msgin()
1234 } else if (code != cmd->device->lun + IDENTIFY_BASE) { in handle_msgin()
1237 "target %d\n", code - IDENTIFY_BASE, in handle_msgin()
1238 cmd->device->lun, ms->conn_tgt); in handle_msgin()
1248 ms->conn_tgt); in handle_msgin()
1249 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1250 printk(" %x", ms->msgin[i]); in handle_msgin()
1252 ms->msgout[0] = MESSAGE_REJECT; in handle_msgin()
1253 ms->n_msgout = 1; in handle_msgin()
1254 ms->msgphase = msg_out; in handle_msgin()
1266 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out? in set_dma_cmds()
1268 dcmds = ms->dma_cmds; in set_dma_cmds()
1273 cmd->SCp.this_residual = scsi_bufflen(cmd); in set_dma_cmds()
1280 off = ms->data_ptr; in set_dma_cmds()
1286 total += scl->length; in set_dma_cmds()
1288 off -= dma_len; in set_dma_cmds()
1293 dcmds->req_count = cpu_to_le16(dma_len - off); in set_dma_cmds()
1294 dcmds->command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1295 dcmds->phy_addr = cpu_to_le32(dma_addr + off); in set_dma_cmds()
1296 dcmds->xfer_status = 0; in set_dma_cmds()
1298 dtot += dma_len - off; in set_dma_cmds()
1309 dcmds->req_count = cpu_to_le16(dtot); in set_dma_cmds()
1310 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf)); in set_dma_cmds()
1311 dcmds->xfer_status = 0; in set_dma_cmds()
1314 dma_cmd += OUTPUT_LAST - OUTPUT_MORE; in set_dma_cmds()
1315 dcmds[-1].command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1317 dcmds->command = cpu_to_le16(DBDMA_STOP); in set_dma_cmds()
1318 ms->dma_count = dtot; in set_dma_cmds()
1323 volatile struct dbdma_regs __iomem *md = ms->dma; in halt_dma()
1324 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma()
1325 struct scsi_cmnd *cmd = ms->current_req; in halt_dma()
1328 if (!ms->tgts[ms->conn_tgt].data_goes_out) { in halt_dma()
1331 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1332 && (in_le32(&md->status) & ACTIVE) != 0) { in halt_dma()
1333 --t; in halt_dma()
1337 out_le32(&md->control, RUN << 16); /* turn off RUN bit */ in halt_dma()
1338 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1340 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1341 if (ms->tgts[ms->conn_tgt].data_goes_out) in halt_dma()
1342 nb += mr->fifo_count; in halt_dma()
1345 ms->data_ptr -= nb; in halt_dma()
1346 dlog(ms, "data_ptr %x", ms->data_ptr); in halt_dma()
1347 if (ms->data_ptr < 0) { in halt_dma()
1349 ms->data_ptr, nb, ms); in halt_dma()
1350 ms->data_ptr = 0; in halt_dma()
1352 dumplog(ms, ms->conn_tgt); in halt_dma()
1356 ms->data_ptr > scsi_bufflen(cmd)) { in halt_dma()
1359 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd), in halt_dma()
1360 ms->tgts[ms->conn_tgt].data_goes_out); in halt_dma()
1364 ms->dma_started = 0; in halt_dma()
1369 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch()
1370 int phase; in phase_mismatch() local
1373 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1374 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1375 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) { in phase_mismatch()
1377 out_8(&mr->count_lo, 1); in phase_mismatch()
1378 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1381 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1382 ms->msgphase = msg_out_last; in phase_mismatch()
1386 if (ms->msgphase == msg_in) { in phase_mismatch()
1388 if (ms->n_msgin) in phase_mismatch()
1392 if (ms->dma_started) in phase_mismatch()
1394 if (mr->fifo_count) { in phase_mismatch()
1395 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1400 ms->msgphase = msg_none; in phase_mismatch()
1401 switch (phase) { in phase_mismatch()
1403 ms->tgts[ms->conn_tgt].data_goes_out = 0; in phase_mismatch()
1404 ms->phase = dataing; in phase_mismatch()
1407 ms->tgts[ms->conn_tgt].data_goes_out = 1; in phase_mismatch()
1408 ms->phase = dataing; in phase_mismatch()
1411 ms->phase = commanding; in phase_mismatch()
1414 ms->phase = statusing; in phase_mismatch()
1417 ms->msgphase = msg_in; in phase_mismatch()
1418 ms->n_msgin = 0; in phase_mismatch()
1421 ms->msgphase = msg_out; in phase_mismatch()
1422 if (ms->n_msgout == 0) { in phase_mismatch()
1423 if (ms->aborting) { in phase_mismatch()
1426 if (ms->last_n_msgout == 0) { in phase_mismatch()
1429 ms->msgout[0] = NOP; in phase_mismatch()
1430 ms->last_n_msgout = 1; in phase_mismatch()
1432 ms->n_msgout = ms->last_n_msgout; in phase_mismatch()
1437 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase); in phase_mismatch()
1438 ms->stat = DID_ERROR; in phase_mismatch()
1448 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete()
1449 struct scsi_cmnd *cmd = ms->current_req; in cmd_complete()
1450 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in cmd_complete()
1453 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1454 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in cmd_complete()
1455 switch (ms->msgphase) { in cmd_complete()
1457 /* huh? we expected a phase mismatch */ in cmd_complete()
1458 ms->n_msgin = 0; in cmd_complete()
1459 ms->msgphase = msg_in; in cmd_complete()
1466 if (ms->n_msgin < n) { in cmd_complete()
1467 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1468 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1470 ms->msgphase = msg_none; in cmd_complete()
1477 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1480 out_8(&mr->count_lo, 1); in cmd_complete()
1481 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1493 * wait for the phase mismatch interrupt, then in cmd_complete()
1496 out_8(&mr->count_lo, 1); in cmd_complete()
1497 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1499 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1502 MKWORD(mr->error, mr->exception, in cmd_complete()
1503 mr->fifo_count, mr->count_lo)); in cmd_complete()
1504 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1506 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1507 ms->n_msgout = 0; in cmd_complete()
1508 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1510 in_8(&mr->error)); in cmd_complete()
1514 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1516 in_8(&mr->exception)); in cmd_complete()
1519 in_8(&mr->bus_status0)); in cmd_complete()
1523 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1524 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1527 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1528 ms->msgphase = msg_out_last; in cmd_complete()
1530 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1531 ms->msgphase = msg_out_xxx; in cmd_complete()
1536 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1537 ms->n_msgout = 0; in cmd_complete()
1538 ms->msgphase = ms->expect_reply? msg_in: msg_none; in cmd_complete()
1543 switch (ms->phase) { in cmd_complete()
1545 printk(KERN_ERR "mesh: interrupt in idle phase?\n"); in cmd_complete()
1549 dlog(ms, "Selecting phase at command completion",0); in cmd_complete()
1550 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt), in cmd_complete()
1551 (cmd? cmd->device->lun: 0)); in cmd_complete()
1552 ms->n_msgout = 1; in cmd_complete()
1553 ms->expect_reply = 0; in cmd_complete()
1554 if (ms->aborting) { in cmd_complete()
1555 ms->msgout[0] = ABORT; in cmd_complete()
1556 ms->n_msgout++; in cmd_complete()
1557 } else if (tp->sdtr_state == do_sdtr) { in cmd_complete()
1560 ms->expect_reply = 1; in cmd_complete()
1561 tp->sdtr_state = sdtr_sent; in cmd_complete()
1563 ms->msgphase = msg_out; in cmd_complete()
1568 * which will give us a phase mismatch interrupt in cmd_complete()
1572 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1573 if (--t < 0) { in cmd_complete()
1574 dlog(ms, "impatient for req", ms->n_msgout); in cmd_complete()
1575 ms->msgphase = msg_none; in cmd_complete()
1582 if (ms->dma_count != 0) { in cmd_complete()
1587 * We can get a phase mismatch here if the target in cmd_complete()
1588 * changes to the status phase, even though we have in cmd_complete()
1594 * error and phase mismatch exception. in cmd_complete()
1596 out_8(&mr->sequence, 0); in cmd_complete()
1597 out_8(&mr->interrupt, in cmd_complete()
1603 cmd->SCp.Status = mr->fifo; in cmd_complete()
1606 cmd->SCp.Status); in cmd_complete()
1608 ms->msgphase = msg_in; in cmd_complete()
1614 ms->current_req = NULL; in cmd_complete()
1615 ms->phase = idle; in cmd_complete()
1621 ++ms->phase; in cmd_complete()
1636 cmd->scsi_done = done; in mesh_queue_lck()
1637 cmd->host_scribble = NULL; in mesh_queue_lck()
1639 ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_queue_lck()
1641 if (ms->request_q == NULL) in mesh_queue_lck()
1642 ms->request_q = cmd; in mesh_queue_lck()
1644 ms->request_qtail->host_scribble = (void *) cmd; in mesh_queue_lck()
1645 ms->request_qtail = cmd; in mesh_queue_lck()
1647 if (ms->phase == idle) in mesh_queue_lck()
1662 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD()
1666 if (ALLOW_DEBUG(ms->conn_tgt)) in DEF_SCSI_QCMD()
1668 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1669 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1670 ms->phase, ms->msgphase); in DEF_SCSI_QCMD()
1672 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1674 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1680 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1692 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_abort()
1696 dumplog(ms, cmd->device->id); in mesh_abort()
1709 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_host_reset()
1710 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset()
1711 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_host_reset()
1716 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_host_reset()
1718 if (ms->dma_started) in mesh_host_reset()
1722 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_host_reset()
1723 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1724 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1725 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1728 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1729 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1730 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1731 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1734 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1737 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1742 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_host_reset()
1751 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1); in set_mesh_power()
1754 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0); in set_mesh_power()
1774 if (ms->phase == sleeping) in mesh_suspend()
1777 scsi_block_requests(ms->host); in mesh_suspend()
1778 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1779 while(ms->phase != idle) { in mesh_suspend()
1780 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1782 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1784 ms->phase = sleeping; in mesh_suspend()
1785 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1786 disable_irq(ms->meshintr); in mesh_suspend()
1797 if (ms->phase != sleeping) in mesh_resume()
1802 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_resume()
1804 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_resume()
1805 enable_irq(ms->meshintr); in mesh_resume()
1806 scsi_unblock_requests(ms->host); in mesh_resume()
1825 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_shutdown()
1826 mr = ms->mesh; in mesh_shutdown()
1827 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1828 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1829 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1832 out_8(&mr->bus_status1, 0); in mesh_shutdown()
1833 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_shutdown()
1862 switch (mdev->bus->chip->type) { in mesh_probe()
1876 return -ENODEV; in mesh_probe()
1881 return -EBUSY; in mesh_probe()
1894 mesh_host->base = macio_resource_start(mdev, 0); in mesh_probe()
1895 mesh_host->irq = macio_irq(mdev, 0); in mesh_probe()
1896 ms = (struct mesh_state *) mesh_host->hostdata; in mesh_probe()
1898 ms->host = mesh_host; in mesh_probe()
1899 ms->mdev = mdev; in mesh_probe()
1900 ms->pdev = pdev; in mesh_probe()
1902 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000); in mesh_probe()
1903 if (ms->mesh == NULL) { in mesh_probe()
1907 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000); in mesh_probe()
1908 if (ms->dma == NULL) { in mesh_probe()
1910 iounmap(ms->mesh); in mesh_probe()
1914 ms->meshintr = macio_irq(mdev, 0); in mesh_probe()
1915 ms->dmaintr = macio_irq(mdev, 1); in mesh_probe()
1920 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd); in mesh_probe()
1923 * enough or until we get some macio-specific versions in mesh_probe()
1925 dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev, in mesh_probe()
1926 ms->dma_cmd_size, &dma_cmd_bus, in mesh_probe()
1933 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space); in mesh_probe()
1934 ms->dma_cmd_space = dma_cmd_space; in mesh_probe()
1935 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds) in mesh_probe()
1936 - (unsigned long)dma_cmd_space; in mesh_probe()
1937 ms->current_req = NULL; in mesh_probe()
1939 ms->tgts[tgt].sdtr_state = do_sdtr; in mesh_probe()
1940 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in mesh_probe()
1941 ms->tgts[tgt].current_req = NULL; in mesh_probe()
1944 if ((cfp = of_get_property(mesh, "clock-frequency", NULL))) in mesh_probe()
1945 ms->clk_freq = *cfp; in mesh_probe()
1948 ms->clk_freq = 50000000; in mesh_probe()
1954 minper = 1000000000 / (ms->clk_freq / 5); /* ns */ in mesh_probe()
1965 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) { in mesh_probe()
1966 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr); in mesh_probe()
1971 if (scsi_add_host(mesh_host, &mdev->ofdev.dev)) in mesh_probe()
1978 free_irq(ms->meshintr, ms); in mesh_probe()
1985 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_probe()
1986 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_probe()
1988 iounmap(ms->dma); in mesh_probe()
1989 iounmap(ms->mesh); in mesh_probe()
1995 return -ENODEV; in mesh_probe()
2001 struct Scsi_Host *mesh_host = ms->host; in mesh_remove()
2005 free_irq(ms->meshintr, ms); in mesh_remove()
2014 iounmap(ms->mesh); in mesh_remove()
2015 iounmap(ms->dma); in mesh_remove()
2018 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_remove()
2019 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_remove()