Lines Matching full:dword
742 u32 reserved2; /* dword 11. rsvd for normal I/O. */
744 u32 addr_low; /* dword 12. rsvd for enc I/O */
745 u32 addr_high; /* dword 13. reserved for enc I/O */
746 __le32 len; /* dword 14: length for normal I/O. */
748 __le32 esgl; /* dword 15. rsvd for enc I/O */
749 __le32 atapi_scsi_cdb[4]; /* dword 16-19. rsvd for enc I/O */
751 __le32 key_index_mode; /* dword 20 */
752 __le32 sector_cnt_enss;/* dword 21 */
753 __le32 keytagl; /* dword 22 */
754 __le32 keytagh; /* dword 23 */
755 __le32 twk_val0; /* dword 24 */
756 __le32 twk_val1; /* dword 25 */
757 __le32 twk_val2; /* dword 26 */
758 __le32 twk_val3; /* dword 27 */
759 __le32 enc_addr_low; /* dword 28. Encryption SGL address high */
760 __le32 enc_addr_high; /* dword 29. Encryption SGL address low */
761 __le32 enc_len; /* dword 30. Encryption length */
762 __le32 enc_esgl; /* dword 31. Encryption esgl bit */
804 __le32 addr_low; /* dword 12: sgl low for normal I/O. */
806 __le32 addr_high; /* dword 13: sgl hi for normal I/O */
808 __le32 len; /* dword 14: len for normal I/O. */
810 __le32 esgl; /* dword 15: ESGL bit for normal I/O. */
813 u8 udt[12]; /* dword 16-18 */
814 __le32 sectcnt_ios; /* dword 19 */
815 __le32 key_cmode; /* dword 20 */
816 __le32 ks_enss; /* dword 21 */
817 __le32 keytagl; /* dword 22 */
818 __le32 keytagh; /* dword 23 */
819 __le32 twk_val0; /* dword 24 */
820 __le32 twk_val1; /* dword 25 */
821 __le32 twk_val2; /* dword 26 */
822 __le32 twk_val3; /* dword 27 */
823 __le32 enc_addr_low; /* dword 28: Encryption sgl addr low */
824 __le32 enc_addr_high; /* dword 29: Encryption sgl addr hi */
825 __le32 enc_len; /* dword 30: Encryption length */
826 __le32 enc_esgl; /* dword 31: ESGL bit for encryption */
1429 #define MAIN_SIGNATURE_OFFSET 0x00 /* DWORD 0x00 */
1430 #define MAIN_INTERFACE_REVISION 0x04 /* DWORD 0x01 */
1431 #define MAIN_FW_REVISION 0x08 /* DWORD 0x02 */
1432 #define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C /* DWORD 0x03 */
1433 #define MAIN_MAX_SGL_OFFSET 0x10 /* DWORD 0x04 */
1434 #define MAIN_CNTRL_CAP_OFFSET 0x14 /* DWORD 0x05 */
1435 #define MAIN_GST_OFFSET 0x18 /* DWORD 0x06 */
1436 #define MAIN_IBQ_OFFSET 0x1C /* DWORD 0x07 */
1437 #define MAIN_OBQ_OFFSET 0x20 /* DWORD 0x08 */
1438 #define MAIN_IQNPPD_HPPD_OFFSET 0x24 /* DWORD 0x09 */
1441 #define MAIN_EVENT_CRC_CHECK 0x48 /* DWORD 0x12 */
1442 #define MAIN_EVENT_LOG_ADDR_HI 0x50 /* DWORD 0x14 */
1443 #define MAIN_EVENT_LOG_ADDR_LO 0x54 /* DWORD 0x15 */
1444 #define MAIN_EVENT_LOG_BUFF_SIZE 0x58 /* DWORD 0x16 */
1445 #define MAIN_EVENT_LOG_OPTION 0x5C /* DWORD 0x17 */
1446 #define MAIN_PCS_EVENT_LOG_ADDR_HI 0x60 /* DWORD 0x18 */
1447 #define MAIN_PCS_EVENT_LOG_ADDR_LO 0x64 /* DWORD 0x19 */
1448 #define MAIN_PCS_EVENT_LOG_BUFF_SIZE 0x68 /* DWORD 0x1A */
1449 #define MAIN_PCS_EVENT_LOG_OPTION 0x6C /* DWORD 0x1B */
1450 #define MAIN_FATAL_ERROR_INTERRUPT 0x70 /* DWORD 0x1C */
1451 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74 /* DWORD 0x1D */
1452 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78 /* DWORD 0x1E */
1453 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C /* DWORD 0x1F */
1454 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80 /* DWORD 0x20 */
1455 #define MAIN_GPIO_LED_FLAGS_OFFSET 0x84 /* DWORD 0x21 */
1456 #define MAIN_ANALOG_SETUP_OFFSET 0x88 /* DWORD 0x22 */
1458 #define MAIN_INT_VECTOR_TABLE_OFFSET 0x8C /* DWORD 0x23 */
1459 #define MAIN_SAS_PHY_ATTR_TABLE_OFFSET 0x90 /* DWORD 0x24 */
1460 #define MAIN_PORT_RECOVERY_TIMER 0x94 /* DWORD 0x25 */
1461 #define MAIN_INT_REASSERTION_DELAY 0x98 /* DWORD 0x26 */
1462 #define MAIN_MPI_ILA_RELEASE_TYPE 0xA4 /* DWORD 0x29 */
1463 #define MAIN_MPI_INACTIVE_FW_VERSION 0XB0 /* DWORD 0x2C */
1492 #define PSPA_PHYSTATE0_OFFSET 0x00 /* Dword V */
1493 #define PSPA_OB_HW_EVENT_PID0_OFFSET 0x04 /* DWORD V+1 */
1494 #define PSPA_PHYSTATE1_OFFSET 0x08 /* Dword V+2 */
1495 #define PSPA_OB_HW_EVENT_PID1_OFFSET 0x0C /* DWORD V+3 */
1496 #define PSPA_PHYSTATE2_OFFSET 0x10 /* Dword V+4 */
1497 #define PSPA_OB_HW_EVENT_PID2_OFFSET 0x14 /* DWORD V+5 */
1498 #define PSPA_PHYSTATE3_OFFSET 0x18 /* Dword V+6 */
1499 #define PSPA_OB_HW_EVENT_PID3_OFFSET 0x1C /* DWORD V+7 */
1500 #define PSPA_PHYSTATE4_OFFSET 0x20 /* Dword V+8 */
1501 #define PSPA_OB_HW_EVENT_PID4_OFFSET 0x24 /* DWORD V+9 */
1502 #define PSPA_PHYSTATE5_OFFSET 0x28 /* Dword V+10 */
1503 #define PSPA_OB_HW_EVENT_PID5_OFFSET 0x2C /* DWORD V+11 */
1504 #define PSPA_PHYSTATE6_OFFSET 0x30 /* Dword V+12 */
1505 #define PSPA_OB_HW_EVENT_PID6_OFFSET 0x34 /* DWORD V+13 */
1506 #define PSPA_PHYSTATE7_OFFSET 0x38 /* Dword V+14 */
1507 #define PSPA_OB_HW_EVENT_PID7_OFFSET 0x3C /* DWORD V+15 */
1508 #define PSPA_PHYSTATE8_OFFSET 0x40 /* DWORD V+16 */
1509 #define PSPA_OB_HW_EVENT_PID8_OFFSET 0x44 /* DWORD V+17 */
1510 #define PSPA_PHYSTATE9_OFFSET 0x48 /* DWORD V+18 */
1511 #define PSPA_OB_HW_EVENT_PID9_OFFSET 0x4C /* DWORD V+19 */
1512 #define PSPA_PHYSTATE10_OFFSET 0x50 /* DWORD V+20 */
1513 #define PSPA_OB_HW_EVENT_PID10_OFFSET 0x54 /* DWORD V+21 */
1514 #define PSPA_PHYSTATE11_OFFSET 0x58 /* DWORD V+22 */
1515 #define PSPA_OB_HW_EVENT_PID11_OFFSET 0x5C /* DWORD V+23 */
1516 #define PSPA_PHYSTATE12_OFFSET 0x60 /* DWORD V+24 */
1517 #define PSPA_OB_HW_EVENT_PID12_OFFSET 0x64 /* DWORD V+25 */
1518 #define PSPA_PHYSTATE13_OFFSET 0x68 /* DWORD V+26 */
1519 #define PSPA_OB_HW_EVENT_PID13_OFFSET 0x6c /* DWORD V+27 */
1520 #define PSPA_PHYSTATE14_OFFSET 0x70 /* DWORD V+28 */
1521 #define PSPA_OB_HW_EVENT_PID14_OFFSET 0x74 /* DWORD V+29 */
1522 #define PSPA_PHYSTATE15_OFFSET 0x78 /* DWORD V+30 */
1523 #define PSPA_OB_HW_EVENT_PID15_OFFSET 0x7c /* DWORD V+31 */