Lines Matching +full:geni +full:- +full:uart
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
7 #include <linux/dma-mapping.h>
14 #include <linux/qcom-geni-se.h>
19 * Generic Interface (GENI) Serial Engine (SE) Wrapper driver is introduced
20 * to manage GENI firmware based Qualcomm Universal Peripheral (QUP) Wrapper
22 * like UART, SPI, I2C, I3C, etc.
28 * GENI based QUP is a highly-flexible and programmable module for supporting
29 * a wide range of serial interfaces like UART, SPI, I2C, I3C, etc. A single
34 * of a DMA Engine and GENI sub modules which enable serial engines to
38 * +-----------------------------------------+
40 * | +----------------------------+ |
41 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
43 * <---Clock Perf.----+ +----+-----------------------+ | |
47 * <--------AHB-------> | | | |
48 * | | +----+ |
51 * <------SE IRQ------+ +----------------------------+ |
53 * +-----------------------------------------+
55 * Figure 1: GENI based QUP Wrapper
57 * The GENI submodules include primary and secondary sequencers which are
59 * master-slave model, primary sequencer drives both TX & RX operations. On
60 * serial interfaces that operate using peer-to-peer model, primary sequencer
67 * GENI SE Wrapper driver is structured into 2 parts:
84 * @struct geni_wrapper - Data structure to represent the QUP Wrapper Core
95 static const char * const icc_path_names[] = {"qup-core", "qup-config",
96 "qup-memory"};
176 * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version
183 struct geni_wrapper *wrapper = se->wrapper; in geni_se_get_qup_hw_version()
185 return readl_relaxed(wrapper->base + QUP_HW_VER_REG); in geni_se_get_qup_hw_version()
224 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
225 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
226 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
227 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR); in geni_se_irq_clear()
228 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR); in geni_se_irq_clear()
229 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN); in geni_se_irq_clear()
233 * geni_se_init() - Initialize the GENI serial engine
236 * @rx_rfr_wm: Ready-for-receive watermark, in units of FIFO words.
238 * This function is used to initialize the GENI serial engine, configure
239 * receive watermark and ready-for-receive watermarks.
246 geni_se_io_init(se->base); in geni_se_init()
247 geni_se_io_set_mode(se->base); in geni_se_init()
249 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG); in geni_se_init()
250 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG); in geni_se_init()
252 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
254 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_init()
256 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
258 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_init()
269 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
274 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_fifo_mode()
276 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
279 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_fifo_mode()
281 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
283 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_fifo_mode()
293 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
298 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN); in geni_se_select_dma_mode()
300 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
303 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN); in geni_se_select_dma_mode()
305 val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
307 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN); in geni_se_select_dma_mode()
311 * geni_se_select_mode() - Select the serial engine transfer mode
336 * GENI FIFO packing is highly configurable. TX/RX packing/unpacking consist
340 * Refer to below examples for detailed bit-field description.
344 * +-----------+-------+-------+-------+-------+
346 * +-----------+-------+-------+-------+-------+
351 * +-----------+-------+-------+-------+-------+
355 * +-----------+-------+-------+-------+-------+
357 * +-----------+-------+-------+-------+-------+
362 * +-----------+-------+-------+-------+-------+
366 * +-----------+-------+-------+-------+-------+
368 * +-----------+-------+-------+-------+-------+
373 * +-----------+-------+-------+-------+-------+
384 * geni_se_config_packing() - Packing configuration of the serial engine
388 * @msb_to_lsb: Transfer from MSB to LSB or vice-versa.
401 int idx_start = msb_to_lsb ? bpw - 1 : 0; in geni_se_config_packing()
403 int idx_delta = msb_to_lsb ? -BITS_PER_BYTE : BITS_PER_BYTE; in geni_se_config_packing()
412 len = min_t(int, temp_bpw, BITS_PER_BYTE) - 1; in geni_se_config_packing()
422 temp_bpw = temp_bpw - BITS_PER_BYTE; in geni_se_config_packing()
425 cfg[iter - 1] |= PACKING_STOP_BIT; in geni_se_config_packing()
430 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0); in geni_se_config_packing()
431 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1); in geni_se_config_packing()
434 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0); in geni_se_config_packing()
435 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1); in geni_se_config_packing()
440 * 0 - 4x8, four words in each entry, max word size of 8 bits in geni_se_config_packing()
441 * 1 - 2x16, two words in each entry, max word size of 16 bits in geni_se_config_packing()
442 * 2 - 1x32, one word in each entry, max word size of 32 bits in geni_se_config_packing()
443 * 3 - undefined in geni_se_config_packing()
446 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN); in geni_se_config_packing()
452 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_off()
454 clk_disable_unprepare(se->clk); in geni_se_clks_off()
455 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_off()
456 wrapper->ahb_clks); in geni_se_clks_off()
460 * geni_se_resources_off() - Turn off resources associated with the serial
470 if (has_acpi_companion(se->dev)) in geni_se_resources_off()
473 ret = pinctrl_pm_select_sleep_state(se->dev); in geni_se_resources_off()
485 struct geni_wrapper *wrapper = se->wrapper; in geni_se_clks_on()
487 ret = clk_bulk_prepare_enable(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
488 wrapper->ahb_clks); in geni_se_clks_on()
492 ret = clk_prepare_enable(se->clk); in geni_se_clks_on()
494 clk_bulk_disable_unprepare(ARRAY_SIZE(wrapper->ahb_clks), in geni_se_clks_on()
495 wrapper->ahb_clks); in geni_se_clks_on()
500 * geni_se_resources_on() - Turn on resources associated with the serial
510 if (has_acpi_companion(se->dev)) in geni_se_resources_on()
517 ret = pinctrl_pm_select_default_state(se->dev); in geni_se_resources_on()
526 * geni_se_clk_tbl_get() - Get the clock table to program DFS
543 if (se->clk_perf_tbl) { in geni_se_clk_tbl_get()
544 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
545 return se->num_clk_levels; in geni_se_clk_tbl_get()
548 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL, in geni_se_clk_tbl_get()
549 sizeof(*se->clk_perf_tbl), in geni_se_clk_tbl_get()
551 if (!se->clk_perf_tbl) in geni_se_clk_tbl_get()
552 return -ENOMEM; in geni_se_clk_tbl_get()
555 freq = clk_round_rate(se->clk, freq + 1); in geni_se_clk_tbl_get()
556 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1]) in geni_se_clk_tbl_get()
558 se->clk_perf_tbl[i] = freq; in geni_se_clk_tbl_get()
560 se->num_clk_levels = i; in geni_se_clk_tbl_get()
561 *tbl = se->clk_perf_tbl; in geni_se_clk_tbl_get()
562 return se->num_clk_levels; in geni_se_clk_tbl_get()
567 * geni_se_clk_freq_match() - Get the matching or closest SE clock frequency
580 * - if @exact is true then @res_freq / <an_integer> == @req_freq
581 * - if @exact is false then @res_freq / <an_integer> <= @req_freq
601 return -EINVAL; in geni_se_clk_freq_match()
606 new_delta = req_freq - tbl[i] / divider; in geni_se_clk_freq_match()
622 return -EINVAL; in geni_se_clk_freq_match()
633 * geni_se_tx_dma_prep() - Prepare the serial engine for TX DMA transfer
646 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_prep()
650 return -EINVAL; in geni_se_tx_dma_prep()
652 *iova = dma_map_single(wrapper->dev, buf, len, DMA_TO_DEVICE); in geni_se_tx_dma_prep()
653 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_tx_dma_prep()
654 return -EIO; in geni_se_tx_dma_prep()
659 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET); in geni_se_tx_dma_prep()
660 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_TX_PTR_L); in geni_se_tx_dma_prep()
661 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_TX_PTR_H); in geni_se_tx_dma_prep()
662 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR); in geni_se_tx_dma_prep()
663 writel(len, se->base + SE_DMA_TX_LEN); in geni_se_tx_dma_prep()
669 * geni_se_rx_dma_prep() - Prepare the serial engine for RX DMA transfer
682 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_prep()
686 return -EINVAL; in geni_se_rx_dma_prep()
688 *iova = dma_map_single(wrapper->dev, buf, len, DMA_FROM_DEVICE); in geni_se_rx_dma_prep()
689 if (dma_mapping_error(wrapper->dev, *iova)) in geni_se_rx_dma_prep()
690 return -EIO; in geni_se_rx_dma_prep()
695 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET); in geni_se_rx_dma_prep()
696 writel_relaxed(lower_32_bits(*iova), se->base + SE_DMA_RX_PTR_L); in geni_se_rx_dma_prep()
697 writel_relaxed(upper_32_bits(*iova), se->base + SE_DMA_RX_PTR_H); in geni_se_rx_dma_prep()
699 writel_relaxed(0, se->base + SE_DMA_RX_ATTR); in geni_se_rx_dma_prep()
700 writel(len, se->base + SE_DMA_RX_LEN); in geni_se_rx_dma_prep()
706 * geni_se_tx_dma_unprep() - Unprepare the serial engine after TX DMA transfer
715 struct geni_wrapper *wrapper = se->wrapper; in geni_se_tx_dma_unprep()
717 if (iova && !dma_mapping_error(wrapper->dev, iova)) in geni_se_tx_dma_unprep()
718 dma_unmap_single(wrapper->dev, iova, len, DMA_TO_DEVICE); in geni_se_tx_dma_unprep()
723 * geni_se_rx_dma_unprep() - Unprepare the serial engine after RX DMA transfer
732 struct geni_wrapper *wrapper = se->wrapper; in geni_se_rx_dma_unprep()
734 if (iova && !dma_mapping_error(wrapper->dev, iova)) in geni_se_rx_dma_unprep()
735 dma_unmap_single(wrapper->dev, iova, len, DMA_FROM_DEVICE); in geni_se_rx_dma_unprep()
742 const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; in geni_icc_get()
744 if (has_acpi_companion(se->dev)) in geni_icc_get()
747 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_get()
751 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); in geni_icc_get()
752 if (IS_ERR(se->icc_paths[i].path)) in geni_icc_get()
759 err = PTR_ERR(se->icc_paths[i].path); in geni_icc_get()
760 if (err != -EPROBE_DEFER) in geni_icc_get()
761 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", in geni_icc_get()
772 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_set_bw()
773 ret = icc_set_bw(se->icc_paths[i].path, in geni_icc_set_bw()
774 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw); in geni_icc_set_bw()
776 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n", in geni_icc_set_bw()
790 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) in geni_icc_set_tag()
791 icc_set_tag(se->icc_paths[i].path, tag); in geni_icc_set_tag()
800 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_enable()
801 ret = icc_enable(se->icc_paths[i].path); in geni_icc_enable()
803 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n", in geni_icc_enable()
817 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { in geni_icc_disable()
818 ret = icc_disable(se->icc_paths[i].path); in geni_icc_disable()
820 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n", in geni_icc_disable()
832 struct device *dev = &pdev->dev; in geni_se_probe()
839 return -ENOMEM; in geni_se_probe()
841 wrapper->dev = dev; in geni_se_probe()
843 wrapper->base = devm_ioremap_resource(dev, res); in geni_se_probe()
844 if (IS_ERR(wrapper->base)) in geni_se_probe()
845 return PTR_ERR(wrapper->base); in geni_se_probe()
847 if (!has_acpi_companion(&pdev->dev)) { in geni_se_probe()
848 wrapper->ahb_clks[0].id = "m-ahb"; in geni_se_probe()
849 wrapper->ahb_clks[1].id = "s-ahb"; in geni_se_probe()
850 ret = devm_clk_bulk_get(dev, NUM_AHB_CLKS, wrapper->ahb_clks); in geni_se_probe()
858 dev_dbg(dev, "GENI SE Driver probed\n"); in geni_se_probe()
863 { .compatible = "qcom,geni-se-qup", },
877 MODULE_DESCRIPTION("GENI Serial Engine Driver");