Lines Matching +full:hdmi +full:- +full:dp3
1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
36 #include <linux/pinctrl/pinconf-generic.h>
51 #include <dt-bindings/interrupt-controller/arm-gic.h>
52 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
53 #include <dt-bindings/gpio/tegra186-gpio.h>
54 #include <dt-bindings/gpio/tegra194-gpio.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
342 * struct tegra_pmc - NVIDIA Tegra PMC
359 * @corereq_high: core power request is active-high
360 * @sysclkreq_high: system clock request is active-high
425 if (pmc->tz_only) { in tegra_pmc_readl()
429 if (pmc->dev) in tegra_pmc_readl()
430 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
440 return readl(pmc->base + offset); in tegra_pmc_readl()
448 if (pmc->tz_only) { in tegra_pmc_writel()
452 if (pmc->dev) in tegra_pmc_writel()
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
460 writel(value, pmc->base + offset); in tegra_pmc_writel()
466 if (pmc->tz_only) in tegra_pmc_scratch_readl()
469 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
475 if (pmc->tz_only) in tegra_pmc_scratch_writel()
478 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
488 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
496 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
501 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
508 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
509 return -EINVAL; in tegra_powergate_lookup()
511 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
515 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
519 return -ENODEV; in tegra_powergate_lookup()
531 * if there is contention with a HW-initiated toggling (i.e. CPU core in tegra20_powergate_set()
532 * power-gated), the command should be retried in that case. in tegra20_powergate_set()
540 } while (ret == -ETIMEDOUT && retries--); in tegra20_powergate_set()
580 * tegra_powergate_set() - set the state of a partition
590 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
591 return -EINVAL; in tegra_powergate_set()
593 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
596 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
600 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
602 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
612 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
619 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
639 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
648 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
649 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_disable_clocks()
657 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
658 err = clk_prepare_enable(pg->clks[i]); in tegra_powergate_enable_clocks()
666 while (i--) in tegra_powergate_enable_clocks()
667 clk_disable_unprepare(pg->clks[i]); in tegra_powergate_enable_clocks()
682 err = reset_control_assert(pg->reset); in tegra_powergate_power_up()
688 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
700 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
706 err = reset_control_deassert(pg->reset); in tegra_powergate_power_up()
712 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
713 err = tegra210_clk_handle_mbist_war(pg->id); in tegra_powergate_power_up()
727 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
742 err = reset_control_assert(pg->reset); in tegra_powergate_power_down()
752 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
761 reset_control_deassert(pg->reset); in tegra_powergate_power_down()
773 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
779 pg->genpd.name, err); in tegra_genpd_power_on()
783 reset_control_release(pg->reset); in tegra_genpd_power_on()
792 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
795 err = reset_control_acquire(pg->reset); in tegra_genpd_power_off()
804 pg->genpd.name, err); in tegra_genpd_power_off()
805 reset_control_release(pg->reset); in tegra_genpd_power_off()
812 * tegra_powergate_power_on() - power on partition
818 return -EINVAL; in tegra_powergate_power_on()
825 * tegra_powergate_power_off() - power off partition
831 return -EINVAL; in tegra_powergate_power_off()
838 * tegra_powergate_is_powered() - check if partition is powered
845 return -EINVAL; in tegra_powergate_is_powered()
851 * tegra_powergate_remove_clamping() - remove power clamps for partition
857 return -EINVAL; in tegra_powergate_remove_clamping()
864 * tegra_powergate_sequence_power_up() - power up partition
878 return -EINVAL; in tegra_powergate_sequence_power_up()
882 return -ENOMEM; in tegra_powergate_sequence_power_up()
884 pg->id = id; in tegra_powergate_sequence_power_up()
885 pg->clks = &clk; in tegra_powergate_sequence_power_up()
886 pg->num_clks = 1; in tegra_powergate_sequence_power_up()
887 pg->reset = rst; in tegra_powergate_sequence_power_up()
888 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
892 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
902 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
912 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
913 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
915 return -EINVAL; in tegra_get_cpu_powergate_id()
919 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
934 * tegra_pmc_cpu_power_on() - power on CPU partition
949 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
969 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
979 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
983 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
1004 seq_printf(s, "------------------\n"); in powergate_show()
1006 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1011 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1022 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
1024 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
1025 return -ENOMEM; in tegra_powergate_debugfs_init()
1039 return -ENODEV; in tegra_powergate_of_get_clks()
1041 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL); in tegra_powergate_of_get_clks()
1042 if (!pg->clks) in tegra_powergate_of_get_clks()
1043 return -ENOMEM; in tegra_powergate_of_get_clks()
1046 pg->clks[i] = of_clk_get(np, i); in tegra_powergate_of_get_clks()
1047 if (IS_ERR(pg->clks[i])) { in tegra_powergate_of_get_clks()
1048 err = PTR_ERR(pg->clks[i]); in tegra_powergate_of_get_clks()
1053 pg->num_clks = count; in tegra_powergate_of_get_clks()
1058 while (i--) in tegra_powergate_of_get_clks()
1059 clk_put(pg->clks[i]); in tegra_powergate_of_get_clks()
1061 kfree(pg->clks); in tegra_powergate_of_get_clks()
1069 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1072 pg->reset = of_reset_control_array_get_exclusive_released(np); in tegra_powergate_of_get_resets()
1073 if (IS_ERR(pg->reset)) { in tegra_powergate_of_get_resets()
1074 err = PTR_ERR(pg->reset); in tegra_powergate_of_get_resets()
1079 err = reset_control_acquire(pg->reset); in tegra_powergate_of_get_resets()
1086 err = reset_control_assert(pg->reset); in tegra_powergate_of_get_resets()
1088 err = reset_control_deassert(pg->reset); in tegra_powergate_of_get_resets()
1092 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1097 reset_control_release(pg->reset); in tegra_powergate_of_get_resets()
1098 reset_control_put(pg->reset); in tegra_powergate_of_get_resets()
1106 struct device *dev = pmc->dev; in tegra_powergate_add()
1113 return -ENOMEM; in tegra_powergate_add()
1115 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1118 err = -ENODEV; in tegra_powergate_add()
1126 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1128 pg->id = id; in tegra_powergate_add()
1129 pg->genpd.name = np->name; in tegra_powergate_add()
1130 pg->genpd.power_off = tegra_genpd_power_off; in tegra_powergate_add()
1131 pg->genpd.power_on = tegra_genpd_power_on; in tegra_powergate_add()
1132 pg->pmc = pmc; in tegra_powergate_add()
1134 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1155 err = pm_genpd_init(&pg->genpd, NULL, off); in tegra_powergate_add()
1162 err = of_genpd_add_provider_simple(np, &pg->genpd); in tegra_powergate_add()
1169 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name); in tegra_powergate_add()
1174 pm_genpd_remove(&pg->genpd); in tegra_powergate_add()
1177 reset_control_put(pg->reset); in tegra_powergate_add()
1180 while (pg->num_clks--) in tegra_powergate_add()
1181 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_add()
1183 kfree(pg->clks); in tegra_powergate_add()
1186 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1221 reset_control_put(pg->reset); in tegra_powergate_remove()
1223 while (pg->num_clks--) in tegra_powergate_remove()
1224 clk_put(pg->clks[pg->num_clks]); in tegra_powergate_remove()
1226 kfree(pg->clks); in tegra_powergate_remove()
1228 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1260 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1261 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1262 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1277 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1278 return -ENOENT; in tegra_io_pad_get_dpd_register_bit()
1281 if (pad->dpd == UINT_MAX) in tegra_io_pad_get_dpd_register_bit()
1282 return -ENOTSUPP; in tegra_io_pad_get_dpd_register_bit()
1284 *mask = BIT(pad->dpd % 32); in tegra_io_pad_get_dpd_register_bit()
1286 if (pad->dpd < 32) { in tegra_io_pad_get_dpd_register_bit()
1287 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1288 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1290 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1291 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1308 if (pmc->clk) { in tegra_io_pad_prepare()
1309 rate = pmc->rate; in tegra_io_pad_prepare()
1311 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1312 return -ENODEV; in tegra_io_pad_prepare()
1341 return -ETIMEDOUT; in tegra_io_pad_poll()
1346 if (pmc->clk) in tegra_io_pad_unprepare()
1351 * tegra_io_pad_power_enable() - enable power to I/O pad
1362 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1366 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1374 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1381 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1387 * tegra_io_pad_power_disable() - disable power to I/O pad
1398 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1402 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1410 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1417 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1446 return -ENOENT; in tegra_io_pad_set_voltage()
1448 if (pad->voltage == UINT_MAX) in tegra_io_pad_set_voltage()
1449 return -ENOTSUPP; in tegra_io_pad_set_voltage()
1451 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1453 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1457 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1459 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1463 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */ in tegra_io_pad_set_voltage()
1465 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1472 value &= ~BIT(pad->voltage); in tegra_io_pad_set_voltage()
1474 value |= BIT(pad->voltage); in tegra_io_pad_set_voltage()
1479 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1493 return -ENOENT; in tegra_io_pad_get_voltage()
1495 if (pad->voltage == UINT_MAX) in tegra_io_pad_get_voltage()
1496 return -ENOTSUPP; in tegra_io_pad_get_voltage()
1498 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1503 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1510 * tegra_io_rail_power_on() - enable power to I/O rail
1522 * tegra_io_rail_power_off() - disable power to I/O rail
1536 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1544 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1559 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1569 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1573 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1588 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) { in tegra_pmc_parse_dt()
1592 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1596 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1600 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1604 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1609 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1611 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value)) in tegra_pmc_parse_dt()
1612 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1614 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1616 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1617 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1619 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1621 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", in tegra_pmc_parse_dt()
1623 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1625 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1626 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1628 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value)) in tegra_pmc_parse_dt()
1629 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1631 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1633 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1634 "nvidia,core-power-req-active-high"); in tegra_pmc_parse_dt()
1636 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1637 "nvidia,sys-clock-req-active-high"); in tegra_pmc_parse_dt()
1639 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1640 "nvidia,combined-power-req"); in tegra_pmc_parse_dt()
1642 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1643 "nvidia,cpu-pwr-good-en"); in tegra_pmc_parse_dt()
1645 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values, in tegra_pmc_parse_dt()
1647 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1648 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1650 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1651 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1658 if (pmc->soc->init) in tegra_pmc_init()
1659 pmc->soc->init(pmc); in tegra_pmc_init()
1666 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1670 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1673 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1675 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1679 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) { in tegra_pmc_init_tsense_reset()
1684 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) { in tegra_pmc_init_tsense_reset()
1685 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1689 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) { in tegra_pmc_init_tsense_reset()
1690 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1694 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) { in tegra_pmc_init_tsense_reset()
1695 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled); in tegra_pmc_init_tsense_reset()
1699 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux)) in tegra_pmc_init_tsense_reset()
1722 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1732 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1742 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
1750 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
1760 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
1785 return -EINVAL; in tegra_io_pad_pinconf_get()
1789 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
1797 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
1805 return -EINVAL; in tegra_io_pad_pinconf_get()
1826 return -EINVAL; in tegra_io_pad_pinconf_set()
1835 err = tegra_io_pad_power_disable(pad->id); in tegra_io_pad_pinconf_set()
1837 err = tegra_io_pad_power_enable(pad->id); in tegra_io_pad_pinconf_set()
1844 return -EINVAL; in tegra_io_pad_pinconf_set()
1845 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
1850 return -EINVAL; in tegra_io_pad_pinconf_set()
1872 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
1875 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
1876 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
1877 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
1879 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
1881 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
1882 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
1883 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
1896 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
1897 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
1898 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
1900 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
1903 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
1913 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
1914 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
1915 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
1917 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
1920 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
1927 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
1930 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
1938 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
1952 if (WARN_ON(fwspec->param_count < 2)) in tegra_pmc_irq_translate()
1953 return -EINVAL; in tegra_pmc_irq_translate()
1955 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
1956 *type = fwspec->param[1]; in tegra_pmc_irq_translate()
1964 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc()
1965 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
1971 return -EINVAL; in tegra_pmc_irq_alloc()
1973 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
1974 const struct tegra_wake_event *event = &soc->wake_events[i]; in tegra_pmc_irq_alloc()
1976 if (fwspec->param_count == 2) { in tegra_pmc_irq_alloc()
1979 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
1983 event->id, in tegra_pmc_irq_alloc()
1984 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1988 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
1991 spec.param[1] = event->irq; in tegra_pmc_irq_alloc()
1992 spec.param[2] = fwspec->param[1]; in tegra_pmc_irq_alloc()
2000 if (fwspec->param_count == 3) { in tegra_pmc_irq_alloc()
2001 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2002 event->gpio.pin != fwspec->param[1]) in tegra_pmc_irq_alloc()
2006 event->id, in tegra_pmc_irq_alloc()
2007 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2010 if (!err && domain->parent) in tegra_pmc_irq_alloc()
2011 err = irq_domain_disconnect_hierarchy(domain->parent, in tegra_pmc_irq_alloc()
2017 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2018 if (i == soc->num_wake_events) in tegra_pmc_irq_alloc()
2035 offset = data->hwirq / 32; in tegra210_pmc_irq_set_wake()
2036 bit = data->hwirq % 32; in tegra210_pmc_irq_set_wake()
2046 if (data->hwirq >= 32) in tegra210_pmc_irq_set_wake()
2069 offset = data->hwirq / 32; in tegra210_pmc_irq_set_type()
2070 bit = data->hwirq % 32; in tegra210_pmc_irq_set_type()
2072 if (data->hwirq >= 32) in tegra210_pmc_irq_set_type()
2095 return -EINVAL; in tegra210_pmc_irq_set_type()
2109 offset = data->hwirq / 32; in tegra186_pmc_irq_set_wake()
2110 bit = data->hwirq % 32; in tegra186_pmc_irq_set_wake()
2113 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2116 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2123 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2126 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2136 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2154 return -EINVAL; in tegra186_pmc_irq_set_type()
2157 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2164 if (data->parent_data) in tegra_irq_mask_parent()
2170 if (data->parent_data) in tegra_irq_unmask_parent()
2176 if (data->parent_data) in tegra_irq_eoi_parent()
2184 if (data->parent_data) in tegra_irq_set_affinity_parent()
2187 return -EINVAL; in tegra_irq_set_affinity_parent()
2195 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2204 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2205 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2206 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2207 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2208 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2209 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2210 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2212 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2214 if (!pmc->domain) { in tegra_pmc_irq_init()
2215 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2216 return -ENOMEM; in tegra_pmc_irq_init()
2230 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2234 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2238 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2243 return notifier_from_errno(-EINVAL); in tegra_pmc_clk_notify_cb()
2261 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2272 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2273 val &= ~(PMC_CLK_OUT_MUX_MASK << clk->mux_shift); in pmc_clk_mux_set_parent()
2274 val |= index << clk->mux_shift; in pmc_clk_mux_set_parent()
2275 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2276 pmc_clk_fence_udelay(clk->offs); in pmc_clk_mux_set_parent()
2286 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2305 pmc_clk_set_state(clk->offs, clk->force_en_shift, 1); in pmc_clk_enable()
2314 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2334 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2336 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_out_register()
2338 init.name = data->name; in tegra_pmc_clk_out_register()
2340 init.parent_names = data->parents; in tegra_pmc_clk_out_register()
2341 init.num_parents = data->num_parents; in tegra_pmc_clk_out_register()
2345 pmc_clk->hw.init = &init; in tegra_pmc_clk_out_register()
2346 pmc_clk->offs = offset; in tegra_pmc_clk_out_register()
2347 pmc_clk->mux_shift = data->mux_shift; in tegra_pmc_clk_out_register()
2348 pmc_clk->force_en_shift = data->force_en_shift; in tegra_pmc_clk_out_register()
2350 return clk_register(NULL, &pmc_clk->hw); in tegra_pmc_clk_out_register()
2357 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2364 pmc_clk_set_state(gate->offs, gate->shift, 1); in pmc_clk_gate_enable()
2373 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2390 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2392 return ERR_PTR(-ENOMEM); in tegra_pmc_clk_gate_register()
2400 gate->hw.init = &init; in tegra_pmc_clk_gate_register()
2401 gate->offs = offset; in tegra_pmc_clk_gate_register()
2402 gate->shift = shift; in tegra_pmc_clk_gate_register()
2404 return clk_register(NULL, &gate->hw); in tegra_pmc_clk_gate_register()
2415 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2416 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2422 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2426 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2427 sizeof(*clk_data->clks), GFP_KERNEL); in tegra_pmc_clock_register()
2428 if (!clk_data->clks) in tegra_pmc_clock_register()
2431 clk_data->clk_num = TEGRA_PMC_CLK_MAX; in tegra_pmc_clock_register()
2434 clk_data->clks[i] = ERR_PTR(-ENOENT); in tegra_pmc_clock_register()
2436 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2439 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2443 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2444 data->name, PTR_ERR_OR_ZERO(clk)); in tegra_pmc_clock_register()
2448 err = clk_register_clkdev(clk, data->name, NULL); in tegra_pmc_clock_register()
2450 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2452 data->name, err); in tegra_pmc_clock_register()
2456 clk_data->clks[data->clk_id] = clk; in tegra_pmc_clock_register()
2459 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2467 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2478 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2486 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2492 clk_data->clks[TEGRA_PMC_CLK_BLINK] = clk; in tegra_pmc_clock_register()
2497 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2512 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2513 return -ENODEV; in tegra_pmc_probe()
2515 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2521 base = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2527 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2528 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2529 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2531 pmc->wake = base; in tegra_pmc_probe()
2536 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2537 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2538 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2540 pmc->aotag = base; in tegra_pmc_probe()
2545 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2546 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2547 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2549 pmc->scratch = base; in tegra_pmc_probe()
2552 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
2553 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
2554 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
2556 if (err != -ENOENT) { in tegra_pmc_probe()
2557 dev_err(&pdev->dev, "failed to get pclk: %d\n", err); in tegra_pmc_probe()
2561 pmc->clk = NULL; in tegra_pmc_probe()
2569 if (pmc->clk) { in tegra_pmc_probe()
2570 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2571 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2573 dev_err(&pdev->dev, in tegra_pmc_probe()
2578 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2581 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2597 dev_err(&pdev->dev, "unable to register restart handler, %d\n", in tegra_pmc_probe()
2606 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2614 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2615 iounmap(pmc->base); in tegra_pmc_probe()
2616 pmc->base = base; in tegra_pmc_probe()
2617 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
2619 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2625 tegra_powergate_remove_all(pdev->dev.of_node); in tegra_pmc_probe()
2629 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
2631 device_remove_file(&pdev->dev, &dev_attr_reset_reason); in tegra_pmc_probe()
2632 device_remove_file(&pdev->dev, &dev_attr_reset_level); in tegra_pmc_probe()
2633 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2695 if (pmc->sysclkreq_high) in tegra20_pmc_init()
2700 if (pmc->corereq_high) in tegra20_pmc_init()
2714 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
2715 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
2716 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
2717 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
2941 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2945 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2947 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2948 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2949 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2950 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3033 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
3042 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
3052 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
3055 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3056 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
3057 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
3058 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3059 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
3063 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
3069 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
3129 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3130 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3131 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3132 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3133 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3137 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
3142 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3143 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3144 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3145 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
3157 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
3159 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3160 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3162 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3163 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3195 index = of_property_match_string(np, "reg-names", "wake"); in tegra186_pmc_setup_irq_polarity()
3197 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3205 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3283 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
3284 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
3285 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
3286 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
3287 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
3289 _pad(TEGRA_IO_PAD_PEX_CLK_2_BIAS, 9, UINT_MAX, "pex-clk-2-bias"), \
3290 _pad(TEGRA_IO_PAD_PEX_CLK_2, 10, UINT_MAX, "pex-clk-2"), \
3294 _pad(TEGRA_IO_PAD_PWR_CTL, 15, UINT_MAX, "pwr-ctl"), \
3295 _pad(TEGRA_IO_PAD_SOC_GPIO53, 16, UINT_MAX, "soc-gpio53"), \
3297 _pad(TEGRA_IO_PAD_GP_PWM2, 18, UINT_MAX, "gp-pwm2"), \
3298 _pad(TEGRA_IO_PAD_GP_PWM3, 19, UINT_MAX, "gp-pwm3"), \
3299 _pad(TEGRA_IO_PAD_SOC_GPIO12, 20, UINT_MAX, "soc-gpio12"), \
3300 _pad(TEGRA_IO_PAD_SOC_GPIO13, 21, UINT_MAX, "soc-gpio13"), \
3301 _pad(TEGRA_IO_PAD_SOC_GPIO10, 22, UINT_MAX, "soc-gpio10"), \
3305 _pad(TEGRA_IO_PAD_HDMI_DP3, 26, UINT_MAX, "hdmi-dp3"), \
3306 _pad(TEGRA_IO_PAD_HDMI_DP2, 27, UINT_MAX, "hdmi-dp2"), \
3307 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
3308 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
3309 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
3310 _pad(TEGRA_IO_PAD_PEX_CTL2, 33, UINT_MAX, "pex-ctl2"), \
3311 _pad(TEGRA_IO_PAD_PEX_L0_RST_N, 34, UINT_MAX, "pex-l0-rst"), \
3312 _pad(TEGRA_IO_PAD_PEX_L1_RST_N, 35, UINT_MAX, "pex-l1-rst"), \
3314 _pad(TEGRA_IO_PAD_PEX_L5_RST_N, 37, UINT_MAX, "pex-l5-rst"), \
3325 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
3326 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
3328 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
3329 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3480 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3481 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3482 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3483 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3484 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3485 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3486 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3487 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3488 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3494 .name = "tegra-pmc",
3509 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3516 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3517 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3519 /* if we read all-zeroes, access is restricted to TZ only */ in tegra_pmc_detect_tz_only()
3526 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3543 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
3548 * Fall back to legacy initialization for 32-bit ARM only. All in tegra_pmc_early_init()
3549 * 64-bit ARM device tree files for Tegra are required to have in tegra_pmc_early_init()
3552 * This is for backwards-compatibility with old device trees in tegra_pmc_early_init()
3568 * nice with multi-platform kernels. in tegra_pmc_early_init()
3580 return -ENXIO; in tegra_pmc_early_init()
3584 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
3585 if (!pmc->base) { in tegra_pmc_early_init()
3588 return -ENXIO; in tegra_pmc_early_init()
3592 pmc->soc = match->data; in tegra_pmc_early_init()
3594 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
3595 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
3598 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3599 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
3600 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
3604 * exists and contains the nvidia,invert-interrupt property. in tegra_pmc_early_init()
3606 invert = of_property_read_bool(np, "nvidia,invert-interrupt"); in tegra_pmc_early_init()
3608 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()