Lines Matching full:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
49 #include <soc/tegra/pmc.h>
55 #include <dt-bindings/soc/tegra-pmc.h>
164 /* for secure PMC */
236 struct tegra_pmc *pmc; member
314 void (*init)(struct tegra_pmc *pmc);
315 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
320 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
342 * struct tegra_pmc - NVIDIA Tegra PMC
343 * @dev: pointer to PMC device structure
350 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
367 * @pctl_dev: pin controller exposed by the PMC
368 * @domain: IRQ domain provided by the PMC
410 static struct tegra_pmc *pmc = &(struct tegra_pmc) { variable
421 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_readl() argument
425 if (pmc->tz_only) { in tegra_pmc_readl()
429 if (pmc->dev) in tegra_pmc_readl()
430 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_readl()
440 return readl(pmc->base + offset); in tegra_pmc_readl()
443 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_writel() argument
448 if (pmc->tz_only) { in tegra_pmc_writel()
452 if (pmc->dev) in tegra_pmc_writel()
453 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n", in tegra_pmc_writel()
460 writel(value, pmc->base + offset); in tegra_pmc_writel()
464 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset) in tegra_pmc_scratch_readl() argument
466 if (pmc->tz_only) in tegra_pmc_scratch_readl()
467 return tegra_pmc_readl(pmc, offset); in tegra_pmc_scratch_readl()
469 return readl(pmc->scratch + offset); in tegra_pmc_scratch_readl()
472 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value, in tegra_pmc_scratch_writel() argument
475 if (pmc->tz_only) in tegra_pmc_scratch_writel()
476 tegra_pmc_writel(pmc, value, offset); in tegra_pmc_scratch_writel()
478 writel(value, pmc->scratch + offset); in tegra_pmc_scratch_writel()
488 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_state()
489 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
491 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
494 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id) in tegra_powergate_is_valid() argument
496 return (pmc->soc && pmc->soc->powergates[id]); in tegra_powergate_is_valid()
499 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id) in tegra_powergate_is_available() argument
501 return test_bit(id, pmc->powergates_available); in tegra_powergate_is_available()
504 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name) in tegra_powergate_lookup() argument
508 if (!pmc || !pmc->soc || !name) in tegra_powergate_lookup()
511 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
512 if (!tegra_powergate_is_valid(pmc, i)) in tegra_powergate_lookup()
515 if (!strcmp(name, pmc->soc->powergates[i])) in tegra_powergate_lookup()
522 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra20_powergate_set() argument
530 * As per TRM documentation, the toggle command will be dropped by PMC in tegra20_powergate_set()
535 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra20_powergate_set()
537 /* wait for PMC to execute the command */ in tegra20_powergate_set()
545 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc) in tegra_powergate_toggle_ready() argument
547 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START); in tegra_powergate_toggle_ready()
550 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra114_powergate_set() argument
556 /* wait while PMC power gating is contended */ in tegra114_powergate_set()
557 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
562 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); in tegra114_powergate_set()
564 /* wait for PMC to accept the command */ in tegra114_powergate_set()
565 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status, in tegra114_powergate_set()
570 /* wait for PMC to execute the command */ in tegra114_powergate_set()
581 * @pmc: power management controller
585 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id, in tegra_powergate_set() argument
590 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps) in tegra_powergate_set()
593 mutex_lock(&pmc->powergates_lock); in tegra_powergate_set()
596 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
600 err = pmc->soc->powergate_set(pmc, id, new_state); in tegra_powergate_set()
602 mutex_unlock(&pmc->powergates_lock); in tegra_powergate_set()
607 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc, in __tegra_powergate_remove_clamping() argument
612 mutex_lock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
619 if (pmc->soc->has_gpu_clamps) { in __tegra_powergate_remove_clamping()
620 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
636 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING); in __tegra_powergate_remove_clamping()
639 mutex_unlock(&pmc->powergates_lock); in __tegra_powergate_remove_clamping()
688 err = tegra_powergate_set(pg->pmc, pg->id, true); in tegra_powergate_power_up()
700 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id); in tegra_powergate_power_up()
712 if (pg->pmc->soc->needs_mbist_war) in tegra_powergate_power_up()
727 tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_up()
752 err = tegra_powergate_set(pg->pmc, pg->id, false); in tegra_powergate_power_down()
773 struct device *dev = pg->pmc->dev; in tegra_genpd_power_on()
792 struct device *dev = pg->pmc->dev; in tegra_genpd_power_off()
817 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_on()
820 return tegra_powergate_set(pmc, id, true); in tegra_powergate_power_on()
830 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_power_off()
833 return tegra_powergate_set(pmc, id, false); in tegra_powergate_power_off()
839 * @pmc: power management controller
842 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id) in tegra_powergate_is_powered() argument
844 if (!tegra_powergate_is_valid(pmc, id)) in tegra_powergate_is_powered()
856 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_remove_clamping()
859 return __tegra_powergate_remove_clamping(pmc, id); in tegra_powergate_remove_clamping()
877 if (!tegra_powergate_is_available(pmc, id)) in tegra_powergate_sequence_power_up()
888 pg->pmc = pmc; in tegra_powergate_sequence_power_up()
892 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id, in tegra_powergate_sequence_power_up()
903 * @pmc: power management controller
909 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc, in tegra_get_cpu_powergate_id() argument
912 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates) in tegra_get_cpu_powergate_id()
913 return pmc->soc->cpu_powergates[cpuid]; in tegra_get_cpu_powergate_id()
926 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_is_powered()
930 return tegra_powergate_is_powered(pmc, id); in tegra_pmc_cpu_is_powered()
941 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_power_on()
945 return tegra_powergate_set(pmc, id, true); in tegra_pmc_cpu_power_on()
956 id = tegra_get_cpu_powergate_id(pmc, cpuid); in tegra_pmc_cpu_remove_clamping()
969 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
983 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0); in tegra_pmc_restart_notify()
986 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_restart_notify()
988 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_restart_notify()
1006 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1007 status = tegra_powergate_is_powered(pmc, i); in powergate_show()
1011 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i], in powergate_show()
1022 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, in tegra_powergate_debugfs_init()
1024 if (!pmc->debugfs) in tegra_powergate_debugfs_init()
1069 struct device *dev = pg->pmc->dev; in tegra_powergate_of_get_resets()
1104 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np) in tegra_powergate_add() argument
1106 struct device *dev = pmc->dev; in tegra_powergate_add()
1115 id = tegra_powergate_lookup(pmc, np->name); in tegra_powergate_add()
1126 clear_bit(id, pmc->powergates_available); in tegra_powergate_add()
1132 pg->pmc = pmc; in tegra_powergate_add()
1134 off = !tegra_powergate_is_powered(pmc, pg->id); in tegra_powergate_add()
1186 set_bit(id, pmc->powergates_available); in tegra_powergate_add()
1194 static int tegra_powergate_init(struct tegra_pmc *pmc, in tegra_powergate_init() argument
1205 err = tegra_powergate_add(pmc, child); in tegra_powergate_init()
1228 set_bit(pg->id, pmc->powergates_available); in tegra_powergate_remove()
1256 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_find() argument
1260 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1261 if (pmc->soc->io_pads[i].id == id) in tegra_io_pad_find()
1262 return &pmc->soc->io_pads[i]; in tegra_io_pad_find()
1267 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc, in tegra_io_pad_get_dpd_register_bit() argument
1275 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_dpd_register_bit()
1277 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id); in tegra_io_pad_get_dpd_register_bit()
1287 *status = pmc->soc->regs->dpd_status; in tegra_io_pad_get_dpd_register_bit()
1288 *request = pmc->soc->regs->dpd_req; in tegra_io_pad_get_dpd_register_bit()
1290 *status = pmc->soc->regs->dpd2_status; in tegra_io_pad_get_dpd_register_bit()
1291 *request = pmc->soc->regs->dpd2_req; in tegra_io_pad_get_dpd_register_bit()
1297 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_prepare() argument
1304 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask); in tegra_io_pad_prepare()
1308 if (pmc->clk) { in tegra_io_pad_prepare()
1309 rate = pmc->rate; in tegra_io_pad_prepare()
1311 dev_err(pmc->dev, "failed to get clock rate\n"); in tegra_io_pad_prepare()
1315 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE); in tegra_io_pad_prepare()
1320 tegra_pmc_writel(pmc, value, SEL_DPD_TIM); in tegra_io_pad_prepare()
1326 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset, in tegra_io_pad_poll() argument
1334 value = tegra_pmc_readl(pmc, offset); in tegra_io_pad_poll()
1344 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc) in tegra_io_pad_unprepare() argument
1346 if (pmc->clk) in tegra_io_pad_unprepare()
1347 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE); in tegra_io_pad_unprepare()
1362 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1364 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); in tegra_io_pad_power_enable()
1366 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1370 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request); in tegra_io_pad_power_enable()
1372 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1374 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err); in tegra_io_pad_power_enable()
1378 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_enable()
1381 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_enable()
1398 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1400 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask); in tegra_io_pad_power_disable()
1402 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1406 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request); in tegra_io_pad_power_disable()
1408 err = tegra_io_pad_poll(pmc, status, mask, mask, 250); in tegra_io_pad_power_disable()
1410 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err); in tegra_io_pad_power_disable()
1414 tegra_io_pad_unprepare(pmc); in tegra_io_pad_power_disable()
1417 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_power_disable()
1422 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_is_powered() argument
1428 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status, in tegra_io_pad_is_powered()
1433 value = tegra_pmc_readl(pmc, status); in tegra_io_pad_is_powered()
1438 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id, in tegra_io_pad_set_voltage() argument
1444 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_set_voltage()
1451 mutex_lock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1453 if (pmc->soc->has_impl_33v_pwr) { in tegra_io_pad_set_voltage()
1454 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1461 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR); in tegra_io_pad_set_voltage()
1464 value = tegra_pmc_readl(pmc, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1466 tegra_pmc_writel(pmc, value, PMC_PWR_DET); in tegra_io_pad_set_voltage()
1469 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1476 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE); in tegra_io_pad_set_voltage()
1479 mutex_unlock(&pmc->powergates_lock); in tegra_io_pad_set_voltage()
1486 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id) in tegra_io_pad_get_voltage() argument
1491 pad = tegra_io_pad_find(pmc, id); in tegra_io_pad_get_voltage()
1498 if (pmc->soc->has_impl_33v_pwr) in tegra_io_pad_get_voltage()
1499 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR); in tegra_io_pad_get_voltage()
1501 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE); in tegra_io_pad_get_voltage()
1536 return pmc->suspend_mode; in tegra_pmc_get_suspend_mode()
1544 pmc->suspend_mode = mode; in tegra_pmc_set_suspend_mode()
1559 rate = pmc->rate; in tegra_pmc_enter_suspend_mode()
1569 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1571 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER); in tegra_pmc_enter_suspend_mode()
1573 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1; in tegra_pmc_enter_suspend_mode()
1575 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER); in tegra_pmc_enter_suspend_mode()
1577 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1580 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra_pmc_enter_suspend_mode()
1584 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np) in tegra_pmc_parse_dt() argument
1592 pmc->suspend_mode = TEGRA_SUSPEND_LP0; in tegra_pmc_parse_dt()
1596 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1600 pmc->suspend_mode = TEGRA_SUSPEND_LP2; in tegra_pmc_parse_dt()
1604 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1609 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode); in tegra_pmc_parse_dt()
1612 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1614 pmc->cpu_good_time = value; in tegra_pmc_parse_dt()
1617 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1619 pmc->cpu_off_time = value; in tegra_pmc_parse_dt()
1623 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1625 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1626 pmc->core_pmu_time = values[1]; in tegra_pmc_parse_dt()
1629 pmc->suspend_mode = TEGRA_SUSPEND_NONE; in tegra_pmc_parse_dt()
1631 pmc->core_off_time = value; in tegra_pmc_parse_dt()
1633 pmc->corereq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1636 pmc->sysclkreq_high = of_property_read_bool(np, in tegra_pmc_parse_dt()
1639 pmc->combined_req = of_property_read_bool(np, in tegra_pmc_parse_dt()
1642 pmc->cpu_pwr_good_en = of_property_read_bool(np, in tegra_pmc_parse_dt()
1647 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0) in tegra_pmc_parse_dt()
1648 pmc->suspend_mode = TEGRA_SUSPEND_LP1; in tegra_pmc_parse_dt()
1650 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1651 pmc->lp0_vec_size = values[1]; in tegra_pmc_parse_dt()
1656 static void tegra_pmc_init(struct tegra_pmc *pmc) in tegra_pmc_init() argument
1658 if (pmc->soc->init) in tegra_pmc_init()
1659 pmc->soc->init(pmc); in tegra_pmc_init()
1662 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc) in tegra_pmc_init_tsense_reset() argument
1666 struct device *dev = pmc->dev; in tegra_pmc_init_tsense_reset()
1670 if (!pmc->soc->has_tsense_reset) in tegra_pmc_init_tsense_reset()
1673 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip"); in tegra_pmc_init_tsense_reset()
1702 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1704 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1708 tegra_pmc_writel(pmc, value, PMC_SCRATCH54); in tegra_pmc_init_tsense_reset()
1726 tegra_pmc_writel(pmc, value, PMC_SCRATCH55); in tegra_pmc_init_tsense_reset()
1728 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1730 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL); in tegra_pmc_init_tsense_reset()
1732 dev_info(pmc->dev, "emergency thermal reset enabled\n"); in tegra_pmc_init_tsense_reset()
1740 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_groups_count() local
1742 return pmc->soc->num_io_pads; in tegra_io_pad_pinctrl_get_groups_count()
1748 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl); in tegra_io_pad_pinctrl_get_group_name() local
1750 return pmc->soc->io_pads[group].name; in tegra_io_pad_pinctrl_get_group_name()
1758 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinctrl_get_group_pins() local
1760 *pins = &pmc->soc->io_pads[group].id; in tegra_io_pad_pinctrl_get_group_pins()
1778 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_get() local
1783 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_get()
1789 ret = tegra_io_pad_get_voltage(pmc, pad->id); in tegra_io_pad_pinconf_get()
1797 ret = tegra_io_pad_is_powered(pmc, pad->id); in tegra_io_pad_pinconf_get()
1817 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev); in tegra_io_pad_pinconf_set() local
1824 pad = tegra_io_pad_find(pmc, pin); in tegra_io_pad_pinconf_set()
1845 err = tegra_io_pad_set_voltage(pmc, pad->id, arg); in tegra_io_pad_pinconf_set()
1868 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc) in tegra_pmc_pinctrl_init() argument
1872 if (!pmc->soc->num_pin_descs) in tegra_pmc_pinctrl_init()
1875 tegra_pmc_pctl_desc.name = dev_name(pmc->dev); in tegra_pmc_pinctrl_init()
1876 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs; in tegra_pmc_pinctrl_init()
1877 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs; in tegra_pmc_pinctrl_init()
1879 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc, in tegra_pmc_pinctrl_init()
1880 pmc); in tegra_pmc_pinctrl_init()
1881 if (IS_ERR(pmc->pctl_dev)) { in tegra_pmc_pinctrl_init()
1882 err = PTR_ERR(pmc->pctl_dev); in tegra_pmc_pinctrl_init()
1883 dev_err(pmc->dev, "failed to register pin controller: %d\n", in tegra_pmc_pinctrl_init()
1896 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_reason_show()
1897 value &= pmc->soc->regs->rst_source_mask; in reset_reason_show()
1898 value >>= pmc->soc->regs->rst_source_shift; in reset_reason_show()
1900 if (WARN_ON(value >= pmc->soc->num_reset_sources)) in reset_reason_show()
1903 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]); in reset_reason_show()
1913 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status); in reset_level_show()
1914 value &= pmc->soc->regs->rst_level_mask; in reset_level_show()
1915 value >>= pmc->soc->regs->rst_level_shift; in reset_level_show()
1917 if (WARN_ON(value >= pmc->soc->num_reset_levels)) in reset_level_show()
1920 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]); in reset_level_show()
1925 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc) in tegra_pmc_reset_sysfs_init() argument
1927 struct device *dev = pmc->dev; in tegra_pmc_reset_sysfs_init()
1930 if (pmc->soc->reset_sources) { in tegra_pmc_reset_sysfs_init()
1938 if (pmc->soc->reset_levels) { in tegra_pmc_reset_sysfs_init()
1964 struct tegra_pmc *pmc = domain->host_data; in tegra_pmc_irq_alloc() local
1965 const struct tegra_pmc_soc *soc = pmc->soc; in tegra_pmc_irq_alloc()
1984 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
1988 spec.fwnode = &pmc->dev->of_node->fwnode; in tegra_pmc_irq_alloc()
2007 &pmc->irq, pmc); in tegra_pmc_irq_alloc()
2009 /* GPIO hierarchies stop at the PMC level */ in tegra_pmc_irq_alloc()
2017 /* If there is no wake-up event, there is no PMC mapping */ in tegra_pmc_irq_alloc()
2031 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_wake() local
2039 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2040 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2042 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2043 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2045 /* enable PMC wake */ in tegra210_pmc_irq_set_wake()
2051 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_wake()
2058 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_wake()
2065 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra210_pmc_irq_set_type() local
2077 value = tegra_pmc_readl(pmc, offset); in tegra210_pmc_irq_set_type()
2098 tegra_pmc_writel(pmc, value, offset); in tegra210_pmc_irq_set_type()
2105 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_wake() local
2113 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2116 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2123 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset)); in tegra186_pmc_irq_set_wake()
2126 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2133 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data); in tegra186_pmc_irq_set_type() local
2136 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2157 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq)); in tegra186_pmc_irq_set_type()
2190 static int tegra_pmc_irq_init(struct tegra_pmc *pmc) in tegra_pmc_irq_init() argument
2195 np = of_irq_find_parent(pmc->dev->of_node); in tegra_pmc_irq_init()
2204 pmc->irq.name = dev_name(pmc->dev); in tegra_pmc_irq_init()
2205 pmc->irq.irq_mask = tegra_irq_mask_parent; in tegra_pmc_irq_init()
2206 pmc->irq.irq_unmask = tegra_irq_unmask_parent; in tegra_pmc_irq_init()
2207 pmc->irq.irq_eoi = tegra_irq_eoi_parent; in tegra_pmc_irq_init()
2208 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent; in tegra_pmc_irq_init()
2209 pmc->irq.irq_set_type = pmc->soc->irq_set_type; in tegra_pmc_irq_init()
2210 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake; in tegra_pmc_irq_init()
2212 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2213 &tegra_pmc_irq_domain_ops, pmc); in tegra_pmc_irq_init()
2214 if (!pmc->domain) { in tegra_pmc_irq_init()
2215 dev_err(pmc->dev, "failed to allocate domain\n"); in tegra_pmc_irq_init()
2225 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb); in tegra_pmc_clk_notify_cb() local
2230 mutex_lock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2234 pmc->rate = data->new_rate; in tegra_pmc_clk_notify_cb()
2238 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_clk_notify_cb()
2251 tegra_pmc_readl(pmc, offset); in pmc_clk_fence_udelay()
2252 /* pmc clk propagation delay 2 us */ in pmc_clk_fence_udelay()
2261 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift; in pmc_clk_mux_get_parent()
2272 val = tegra_pmc_readl(pmc, clk->offs); in pmc_clk_mux_set_parent()
2275 tegra_pmc_writel(pmc, val, clk->offs); in pmc_clk_mux_set_parent()
2286 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift); in pmc_clk_is_enabled()
2295 val = tegra_pmc_readl(pmc, offs); in pmc_clk_set_state()
2297 tegra_pmc_writel(pmc, val, offs); in pmc_clk_set_state()
2327 tegra_pmc_clk_out_register(struct tegra_pmc *pmc, in tegra_pmc_clk_out_register() argument
2334 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL); in tegra_pmc_clk_out_register()
2357 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2383 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name, in tegra_pmc_clk_gate_register() argument
2390 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL); in tegra_pmc_clk_gate_register()
2407 static void tegra_pmc_clock_register(struct tegra_pmc *pmc, in tegra_pmc_clock_register() argument
2415 num_clks = pmc->soc->num_pmc_clks; in tegra_pmc_clock_register()
2416 if (pmc->soc->has_blink_output) in tegra_pmc_clock_register()
2422 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL); in tegra_pmc_clock_register()
2426 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX, in tegra_pmc_clock_register()
2436 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2439 data = pmc->soc->pmc_clks_data + i; in tegra_pmc_clock_register()
2441 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL); in tegra_pmc_clock_register()
2443 dev_warn(pmc->dev, "unable to register clock %s: %d\n", in tegra_pmc_clock_register()
2450 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2459 if (pmc->soc->has_blink_output) { in tegra_pmc_clock_register()
2460 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2461 clk = tegra_pmc_clk_gate_register(pmc, in tegra_pmc_clock_register()
2467 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2473 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink", in tegra_pmc_clock_register()
2478 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2486 dev_warn(pmc->dev, in tegra_pmc_clock_register()
2497 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n", in tegra_pmc_clock_register()
2512 if (WARN_ON(!pmc->base || !pmc->soc)) in tegra_pmc_probe()
2515 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2527 pmc->wake = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2528 if (IS_ERR(pmc->wake)) in tegra_pmc_probe()
2529 return PTR_ERR(pmc->wake); in tegra_pmc_probe()
2531 pmc->wake = base; in tegra_pmc_probe()
2536 pmc->aotag = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2537 if (IS_ERR(pmc->aotag)) in tegra_pmc_probe()
2538 return PTR_ERR(pmc->aotag); in tegra_pmc_probe()
2540 pmc->aotag = base; in tegra_pmc_probe()
2545 pmc->scratch = devm_ioremap_resource(&pdev->dev, res); in tegra_pmc_probe()
2546 if (IS_ERR(pmc->scratch)) in tegra_pmc_probe()
2547 return PTR_ERR(pmc->scratch); in tegra_pmc_probe()
2549 pmc->scratch = base; in tegra_pmc_probe()
2552 pmc->clk = devm_clk_get(&pdev->dev, "pclk"); in tegra_pmc_probe()
2553 if (IS_ERR(pmc->clk)) { in tegra_pmc_probe()
2554 err = PTR_ERR(pmc->clk); in tegra_pmc_probe()
2561 pmc->clk = NULL; in tegra_pmc_probe()
2569 if (pmc->clk) { in tegra_pmc_probe()
2570 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb; in tegra_pmc_probe()
2571 err = clk_notifier_register(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2578 pmc->rate = clk_get_rate(pmc->clk); in tegra_pmc_probe()
2581 pmc->dev = &pdev->dev; in tegra_pmc_probe()
2583 tegra_pmc_init(pmc); in tegra_pmc_probe()
2585 tegra_pmc_init_tsense_reset(pmc); in tegra_pmc_probe()
2587 tegra_pmc_reset_sysfs_init(pmc); in tegra_pmc_probe()
2602 err = tegra_pmc_pinctrl_init(pmc); in tegra_pmc_probe()
2606 err = tegra_powergate_init(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2610 err = tegra_pmc_irq_init(pmc); in tegra_pmc_probe()
2614 mutex_lock(&pmc->powergates_lock); in tegra_pmc_probe()
2615 iounmap(pmc->base); in tegra_pmc_probe()
2616 pmc->base = base; in tegra_pmc_probe()
2617 mutex_unlock(&pmc->powergates_lock); in tegra_pmc_probe()
2619 tegra_pmc_clock_register(pmc, pdev->dev.of_node); in tegra_pmc_probe()
2620 platform_set_drvdata(pdev, pmc); in tegra_pmc_probe()
2629 debugfs_remove(pmc->debugfs); in tegra_pmc_probe()
2633 clk_notifier_unregister(pmc->clk, &pmc->clk_nb); in tegra_pmc_probe()
2641 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_suspend() local
2643 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41); in tegra_pmc_suspend()
2650 struct tegra_pmc *pmc = dev_get_drvdata(dev); in tegra_pmc_resume() local
2652 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
2684 static void tegra20_pmc_init(struct tegra_pmc *pmc) in tegra20_pmc_init() argument
2689 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2691 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2693 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2695 if (pmc->sysclkreq_high) in tegra20_pmc_init()
2700 if (pmc->corereq_high) in tegra20_pmc_init()
2706 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2709 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_init()
2711 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_init()
2714 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) { in tegra20_pmc_init()
2715 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000); in tegra20_pmc_init()
2716 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000); in tegra20_pmc_init()
2717 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000); in tegra20_pmc_init()
2718 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
2720 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER); in tegra20_pmc_init()
2724 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra20_pmc_setup_irq_polarity() argument
2730 value = tegra_pmc_readl(pmc, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
2737 tegra_pmc_writel(pmc, value, PMC_CNTRL); in tegra20_pmc_setup_irq_polarity()
3186 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc, in tegra186_pmc_setup_irq_polarity() argument
3197 dev_err(pmc->dev, "failed to find PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3205 dev_err(pmc->dev, "failed to map PMC wake registers\n"); in tegra186_pmc_setup_irq_polarity()
3480 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
3481 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
3482 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
3483 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
3484 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
3485 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
3486 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
3487 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
3488 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
3494 .name = "tegra-pmc",
3505 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc) in tegra_pmc_detect_tz_only() argument
3509 saved = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3516 writel(value, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3517 value = readl(pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3521 pr_info("access to PMC is restricted to TZ\n"); in tegra_pmc_detect_tz_only()
3526 writel(saved, pmc->base + pmc->soc->regs->scratch0); in tegra_pmc_detect_tz_only()
3543 mutex_init(&pmc->powergates_lock); in tegra_pmc_early_init()
3550 * a PMC node. in tegra_pmc_early_init()
3553 * that didn't contain a PMC node. Note that in this case the in tegra_pmc_early_init()
3578 pr_err("failed to get PMC registers\n"); in tegra_pmc_early_init()
3584 pmc->base = ioremap(regs.start, resource_size(®s)); in tegra_pmc_early_init()
3585 if (!pmc->base) { in tegra_pmc_early_init()
3586 pr_err("failed to map PMC registers\n"); in tegra_pmc_early_init()
3592 pmc->soc = match->data; in tegra_pmc_early_init()
3594 if (pmc->soc->maybe_tz_only) in tegra_pmc_early_init()
3595 pmc->tz_only = tegra_pmc_detect_tz_only(pmc); in tegra_pmc_early_init()
3598 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3599 if (pmc->soc->powergates[i]) in tegra_pmc_early_init()
3600 set_bit(i, pmc->powergates_available); in tegra_pmc_early_init()
3603 * Invert the interrupt polarity if a PMC device tree node in tegra_pmc_early_init()
3608 pmc->soc->setup_irq_polarity(pmc, np, invert); in tegra_pmc_early_init()