1 // SPDX-License-Identifier: GPL-2.0+
3  * Voltage regulators coupler for NVIDIA Tegra20
4  * Copyright (C) 2019 GRATE-DRIVER project
7  * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt)	"tegra voltage-coupler: " fmt
41 	if (tegra->core_min_uV > 0)  in tegra20_core_limit()
42 		return tegra->core_min_uV;  in tegra20_core_limit()
57 	 * whatever maximum value defined via board's device-tree.  in tegra20_core_limit()
59 	tegra->core_min_uV = core_max_uV;  in tegra20_core_limit()
61 	pr_info("core minimum voltage limited to %duV\n", tegra->core_min_uV);  in tegra20_core_limit()
63 	return tegra->core_min_uV;  in tegra20_core_limit()
69 	struct coupling_desc *c_desc = &core_rdev->coupling_desc;  in tegra20_core_rtc_max_spread()
74 	for (i = 1; i < c_desc->n_coupled; i++) {  in tegra20_core_rtc_max_spread()
75 		max_spread = core_rdev->constraints->max_spread[i - 1];  in tegra20_core_rtc_max_spread()
76 		rdev = c_desc->coupled_rdevs[i];  in tegra20_core_rtc_max_spread()
82 	pr_err_once("rtc-core max-spread is undefined in device-tree\n");  in tegra20_core_rtc_max_spread()
102 	 * RTC and CORE voltages should be no more than 170mV from each other,  in tegra20_core_rtc_update()
103 	 * CPU should be below RTC and CORE by at least 120mV. This applies  in tegra20_core_rtc_update()
104 	 * to all Tegra20 SoC's.  in tegra20_core_rtc_update()
132 		return -EINVAL;  in tegra20_core_rtc_update()
135 		pr_err("core-cpu voltage constraint violated: %d %d\n",  in tegra20_core_rtc_update()
143 		pr_err("rtc-cpu voltage constraint violated: %d %d\n",  in tegra20_core_rtc_update()
146 	if (abs(core_uV - rtc_uV) > 170000)  in tegra20_core_rtc_update()
147 		pr_err("core-rtc voltage constraint violated: %d %d\n",  in tegra20_core_rtc_update()
150 	rtc_min_uV = max(cpu_min_uV + 125000, core_min_uV - max_spread);  in tegra20_core_rtc_update()
161 			core_target_uV = max(core_uV - max_spread, core_min_uV);  in tegra20_core_rtc_update()
162 			core_target_uV = max(rtc_uV - max_spread, core_target_uV);  in tegra20_core_rtc_update()
181 			rtc_target_uV = max(rtc_uV - max_spread, rtc_min_uV);  in tegra20_core_rtc_update()
182 			rtc_target_uV = max(core_uV - max_spread, rtc_target_uV);  in tegra20_core_rtc_update()
283 	struct regulator_dev *core_rdev = tegra->core_rdev;  in tegra20_regulator_balance_voltage()
284 	struct regulator_dev *cpu_rdev = tegra->cpu_rdev;  in tegra20_regulator_balance_voltage()
285 	struct regulator_dev *rtc_rdev = tegra->rtc_rdev;  in tegra20_regulator_balance_voltage()
290 		return -EINVAL;  in tegra20_regulator_balance_voltage()
303 	return -EPERM;  in tegra20_regulator_balance_voltage()
310 	struct device_node *np = rdev->dev.of_node;  in tegra20_regulator_attach()
312 	if (of_property_read_bool(np, "nvidia,tegra-core-regulator") &&  in tegra20_regulator_attach()
313 	    !tegra->core_rdev) {  in tegra20_regulator_attach()
314 		tegra->core_rdev = rdev;  in tegra20_regulator_attach()
318 	if (of_property_read_bool(np, "nvidia,tegra-rtc-regulator") &&  in tegra20_regulator_attach()
319 	    !tegra->rtc_rdev) {  in tegra20_regulator_attach()
320 		tegra->rtc_rdev = rdev;  in tegra20_regulator_attach()
324 	if (of_property_read_bool(np, "nvidia,tegra-cpu-regulator") &&  in tegra20_regulator_attach()
325 	    !tegra->cpu_rdev) {  in tegra20_regulator_attach()
326 		tegra->cpu_rdev = rdev;  in tegra20_regulator_attach()
330 	return -EINVAL;  in tegra20_regulator_attach()
338 	if (tegra->core_rdev == rdev) {  in tegra20_regulator_detach()
339 		tegra->core_rdev = NULL;  in tegra20_regulator_detach()
343 	if (tegra->rtc_rdev == rdev) {  in tegra20_regulator_detach()
344 		tegra->rtc_rdev = NULL;  in tegra20_regulator_detach()
348 	if (tegra->cpu_rdev == rdev) {  in tegra20_regulator_detach()
349 		tegra->cpu_rdev = NULL;  in tegra20_regulator_detach()
353 	return -EINVAL;  in tegra20_regulator_detach()
366 	if (!of_machine_is_compatible("nvidia,tegra20"))  in tegra_regulator_coupler_init()