83 /* MSPI register offsets */
170 	MSPI,  enumerator
567 /* MSPI helpers */
577 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);  in bcm_qspi_hw_set_parms()
590 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);  in bcm_qspi_hw_set_parms()
603 			bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);  in bcm_qspi_hw_set_parms()
606 		bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);  in bcm_qspi_hw_set_parms()
699 	return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;  in read_rxram_slot_u8()
708 	return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |  in read_rxram_slot_u16()
709 		((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);  in read_rxram_slot_u16()
758 	bcm_qspi_write(qspi, MSPI, reg_offset, val);  in write_txram_slot_u8()
768 	bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));  in write_txram_slot_u16()
769 	bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));  in write_txram_slot_u16()
774 	return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));  in read_cdram_slot()
779 	bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);  in write_cdram_slot()
832 	bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);  in write_to_hw()
833 	bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);  in write_to_hw()
851 		bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);  in write_to_hw()
853 	/* Must flush previous writes before starting MSPI operation */  in write_to_hw()
856 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);  in write_to_hw()
878 	bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);  in bcm_qspi_bspi_exec_mem_op()
924 			 * clear soc MSPI and BSPI interrupts and enable  in bcm_qspi_bspi_exec_mem_op()
966 			dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");  in bcm_qspi_transfer_one()
999 	/* lets mspi know that this is not last transfer */  in bcm_qspi_mspi_exec_mem_op()
1040 		 * using MSPI.  in bcm_qspi_exec_mem_op()
1049 	/* non-aligned and very short transfers are handled by MSPI */  in bcm_qspi_exec_mem_op()
1076 	u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);  in bcm_qspi_mspi_l2_isr()
1082 		bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);  in bcm_qspi_mspi_l2_isr()
1236 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);  in bcm_qspi_hw_init()
1237 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);  in bcm_qspi_hw_init()
1238 	bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);  in bcm_qspi_hw_init()
1239 	bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);  in bcm_qspi_hw_init()
1240 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);  in bcm_qspi_hw_init()
1253 	u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);  in bcm_qspi_hw_uninit()
1255 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);  in bcm_qspi_hw_uninit()
1257 		bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);  in bcm_qspi_hw_uninit()
1260 	bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);  in bcm_qspi_hw_uninit()
1370 						   "mspi");  in bcm_qspi_probe()
1372 	qspi->base[MSPI]  = devm_ioremap_resource(dev, res);  in bcm_qspi_probe()
1373 	if (IS_ERR(qspi->base[MSPI]))  in bcm_qspi_probe()
1374 		return PTR_ERR(qspi->base[MSPI]);  in bcm_qspi_probe()
1423 		rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);  in bcm_qspi_probe()
1448 			/* all mspi, bspi intrs muxed to one L1 intr */  in bcm_qspi_probe()
1545 		/* enable MSPI interrupt */  in bcm_qspi_resume()