Lines Matching +full:rclk +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
32 #define CQSPI_NAME "cadence-qspi"
248 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
255 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
267 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
270 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
275 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
284 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
285 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
286 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
314 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
317 return -ETIMEDOUT; in cqspi_wait_idle()
326 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
339 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
351 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
352 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
353 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
354 u8 opcode = op->cmd.opcode; in cqspi_command_read()
355 size_t n_rx = op->data.nbytes; in cqspi_command_read()
362 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
365 return -EINVAL; in cqspi_command_read()
376 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
392 read_len = n_rx - read_len; in cqspi_command_read()
402 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
403 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
404 const u8 opcode = op->cmd.opcode; in cqspi_command_write()
405 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
406 size_t n_tx = op->data.nbytes; in cqspi_command_write()
412 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
415 return -EINVAL; in cqspi_command_write()
420 if (op->addr.nbytes) { in cqspi_command_write()
422 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
426 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
431 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
441 write_len = n_tx - 4; in cqspi_command_write()
453 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
454 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
458 reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB; in cqspi_read_setup()
462 dummy_clk = op->dummy.nbytes * 8; in cqspi_read_setup()
464 return -EOPNOTSUPP; in cqspi_read_setup()
475 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
484 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
485 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
486 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
487 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
502 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
507 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
509 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
521 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
534 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
538 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
543 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
576 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
577 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
580 reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; in cqspi_write_setup()
587 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
596 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
597 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
598 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
611 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
621 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
622 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
632 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
639 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
643 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
646 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
650 remaining -= write_bytes; in cqspi_indirect_write_execute()
653 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
686 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
687 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
688 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
692 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
726 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
727 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
728 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
734 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
736 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
741 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
742 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
743 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
758 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
759 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
763 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
775 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
796 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
812 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
813 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
814 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
821 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
827 cqspi->sclk = sclk; in cqspi_configure()
830 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
831 f_pdata->read_delay); in cqspi_configure()
841 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
842 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
843 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
845 if (op->data.dir == SPI_MEM_DATA_IN) { in cqspi_set_protocol()
846 switch (op->data.buswidth) { in cqspi_set_protocol()
848 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
851 f_pdata->data_width = CQSPI_INST_TYPE_DUAL; in cqspi_set_protocol()
854 f_pdata->data_width = CQSPI_INST_TYPE_QUAD; in cqspi_set_protocol()
857 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; in cqspi_set_protocol()
860 return -EINVAL; in cqspi_set_protocol()
870 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
871 loff_t to = op->addr.val; in cqspi_write()
872 size_t len = op->data.nbytes; in cqspi_write()
873 const u_char *buf = op->data.buf.out; in cqspi_write()
884 if (cqspi->use_direct_mode && ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
885 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
896 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
902 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
903 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
905 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
912 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
913 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
917 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
921 return -ENOMEM; in cqspi_direct_read_execute()
923 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
927 ret = -EIO; in cqspi_direct_read_execute()
931 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
932 tx->callback_param = cqspi; in cqspi_direct_read_execute()
933 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
934 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
939 ret = -EIO; in cqspi_direct_read_execute()
943 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
944 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
946 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
948 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
961 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
962 loff_t from = op->addr.val; in cqspi_read()
963 size_t len = op->data.nbytes; in cqspi_read()
964 u_char *buf = op->data.buf.in; in cqspi_read()
975 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
983 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_mem_process()
986 f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; in cqspi_mem_process()
987 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
989 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
990 if (!op->addr.nbytes) in cqspi_mem_process()
996 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1008 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1017 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1018 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1019 return -ENXIO; in cqspi_of_get_flash_pdata()
1022 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1023 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1024 return -ENXIO; in cqspi_of_get_flash_pdata()
1027 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1028 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1029 return -ENXIO; in cqspi_of_get_flash_pdata()
1032 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1033 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1034 return -ENXIO; in cqspi_of_get_flash_pdata()
1037 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1038 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1039 return -ENXIO; in cqspi_of_get_flash_pdata()
1042 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1043 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1044 return -ENXIO; in cqspi_of_get_flash_pdata()
1052 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1053 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1055 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1057 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1058 dev_err(dev, "couldn't determine fifo-depth\n"); in cqspi_of_get_pdata()
1059 return -ENXIO; in cqspi_of_get_pdata()
1062 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1063 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1064 return -ENXIO; in cqspi_of_get_pdata()
1067 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1068 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1069 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1070 return -ENXIO; in cqspi_of_get_pdata()
1073 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1085 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1088 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1091 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1094 writel(cqspi->trigger_address, in cqspi_controller_init()
1095 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1097 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1098 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1099 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1100 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1101 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1102 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1105 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1107 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1119 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1120 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1121 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1122 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1123 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1125 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1132 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_get_name()
1133 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1135 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); in cqspi_get_name()
1145 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1146 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1147 struct device_node *np = dev->of_node; in cqspi_setup_flash()
1153 for_each_available_child_of_node(dev->of_node, np) { in cqspi_setup_flash()
1162 return -EINVAL; in cqspi_setup_flash()
1165 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1166 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1167 f_pdata->cs = cs; in cqspi_setup_flash()
1181 struct device *dev = &pdev->dev; in cqspi_probe()
1189 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1191 dev_err(&pdev->dev, "spi_alloc_master failed\n"); in cqspi_probe()
1192 return -ENOMEM; in cqspi_probe()
1194 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1195 master->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1196 master->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1200 cqspi->pdev = pdev; in cqspi_probe()
1207 ret = -ENODEV; in cqspi_probe()
1212 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1213 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1215 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1221 cqspi->iobase = devm_ioremap_resource(dev, res); in cqspi_probe()
1222 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1224 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1230 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); in cqspi_probe()
1231 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1233 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1236 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1237 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1239 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1244 ret = -ENXIO; in cqspi_probe()
1255 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1269 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1282 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1285 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1286 cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1287 cqspi->master_ref_clk_hz); in cqspi_probe()
1288 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1289 master->mode_bits |= SPI_RX_OCTAL; in cqspi_probe()
1290 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) in cqspi_probe()
1291 cqspi->use_direct_mode = true; in cqspi_probe()
1295 pdev->name, cqspi); in cqspi_probe()
1303 cqspi->current_cs = -1; in cqspi_probe()
1304 cqspi->sclk = 0; in cqspi_probe()
1312 if (cqspi->use_direct_mode) { in cqspi_probe()
1314 if (ret == -EPROBE_DEFER) in cqspi_probe()
1320 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1328 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1343 if (cqspi->rx_chan) in cqspi_remove()
1344 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1346 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1348 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1349 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1364 clk_disable_unprepare(cqspi->clk); in cqspi_suspend()
1374 clk_prepare_enable(cqspi->clk); in cqspi_resume()
1378 cqspi->current_cs = -1; in cqspi_resume()
1379 cqspi->sclk = 0; in cqspi_resume()
1409 .compatible = "cdns,qspi-nor",
1413 .compatible = "ti,k2g-qspi",
1417 .compatible = "ti,am654-ospi",